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linux/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi
Martyn Welch ab4d874c9f arm64: dts: imx8mp: Add device tree for Nitrogen8M Plus ENC Carrier Board 
Add support for Boundary Devices/Ezurio Nitrogen8M Plus ENC Carrier
Board and it's SOM. Supported interfaces:

 - Serial Console
 - EQoS Ethernet
 - USB
 - eMMC
 - HDMI

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-25 08:36:43 +08:00

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Boundary Devices
* Copyright 2025 Collabora Ltd.
*/
#include "imx8mp.dtsi"
/ {
model = "Boundary Devices Nitrogen8M Plus Som";
compatible = "boundary,imx8mp-nitrogen-som", "fsl,imx8mp";
rfkill-bt {
compatible = "rfkill-gpio";
label = "rfkill-bluetooth";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rfkill_bt>;
radio-type = "bluetooth";
shutdown-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
};
rfkill-wlan {
compatible = "rfkill-gpio";
label = "rfkill-wlan";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rfkill_wlan>;
radio-type = "wlan";
shutdown-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&eqos {
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
eee-broken-1000t;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_OPEN_DRAIN>;
sda-gpios = <&gpio5 15 GPIO_OPEN_DRAIN>;
status = "okay";
pmic: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
interrupt-parent = <&gpio3>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_pmic>;
regulators {
buck1: BUCK1 {
regulator-name = "VDD_SOC (BUCK1)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "VDD_ARM (BUCK2)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-name = "VDD_3P3V (BUCK4)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
buck5: BUCK5 {
regulator-name = "VDD_1P8V (BUCK5)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
buck6: BUCK6 {
regulator-name = "NVCC_DRAM_1P1V (BUCK6)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
ldo1: LDO1 {
regulator-name = "NVCC_SNVS_1V8 (LDO1)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
};
ldo3: LDO3 {
regulator-name = "VDDA_1V8 (LDO3)";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
};
ldo5: LDO5 {
regulator-name = "NVCC_SD1 (LDO5)";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 GPIO_OPEN_DRAIN>;
sda-gpios = <&gpio5 17 GPIO_OPEN_DRAIN>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 GPIO_OPEN_DRAIN>;
sda-gpios = <&gpio5 19 GPIO_OPEN_DRAIN>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 GPIO_OPEN_DRAIN>;
sda-gpios = <&gpio5 21 GPIO_OPEN_DRAIN>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc2 {
bus-width = <4>;
keep-power-in-suspend;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
status = "okay";
};
&usdhc3 {
bus-width = <8>;
non-removable;
no-mmc-hs400;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x20
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0xa0
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x10
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x100
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41
>;
};
pinctrl_rfkill_bt: rfkill-btgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119
>;
};
pinctrl_rfkill_wlan: rfkill-wlangrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x16
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x10
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x150
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x150
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x150
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x150
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x150
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x150
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x150
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x150
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x150
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x140
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x14
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x154
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x154
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x154
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x154
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x154
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x154
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x154
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x154
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x154
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x12
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x152
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x152
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x152
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x152
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x152
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x152
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x152
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x152
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x152
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};
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