mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-09-18 22:14:16 +00:00
7b17f5ebd5
New SoC support for Broadcom bcm2712 (Raspberry Pi 5) and Renesas
R9A09G057 (RZ/V2H(P)) and Qualcomm Snapdragon 414 (MSM8929), all three
of these are variants of already supported chips, in particular the last
one is almost identical to MSM8939.
Lots of updates to Mediatek, ASpeed, Rockchips, Amlogic, Qualcomm,
STM32, NXP i.MX, Sophgo, TI K3, Renesas, Microchip at91, NVIDIA Tegra,
and T-HEAD.
The added Qualcomm platform support once again dominates the changes,
with seven phones and three laptops getting added in addition to
many new features on existing machines. The Snapdragon X1E support
specifically keeps improving.
The other new machines are:
- eight new machines using various 64-bit Rockchips SoCs, both
on the consumer/gaming side and developer boards
- three industrial boards with 64-bit i.MX, which is a very
low number for them.
- four more servers using a 32-bit Speed BMC
- three boards using STM32MP1 SoCs
- one new machine each using allwinner, amlogic, broadcom
and renesas chips.
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Merge tag 'soc-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"New SoC support for Broadcom bcm2712 (Raspberry Pi 5) and Renesas
R9A09G057 (RZ/V2H(P)) and Qualcomm Snapdragon 414 (MSM8929), all three
of these are variants of already supported chips, in particular the
last one is almost identical to MSM8939.
Lots of updates to Mediatek, ASpeed, Rockchips, Amlogic, Qualcomm,
STM32, NXP i.MX, Sophgo, TI K3, Renesas, Microchip at91, NVIDIA Tegra,
and T-HEAD.
The added Qualcomm platform support once again dominates the changes,
with seven phones and three laptops getting added in addition to many
new features on existing machines. The Snapdragon X1E support
specifically keeps improving.
The other new machines are:
- eight new machines using various 64-bit Rockchips SoCs, both on the
consumer/gaming side and developer boards
- three industrial boards with 64-bit i.MX, which is a very low
number for them.
- four more servers using a 32-bit Speed BMC
- three boards using STM32MP1 SoCs
- one new machine each using allwinner, amlogic, broadcom and renesas
chips"
* tag 'soc-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (672 commits)
arm64: dts: allwinner: h5: NanoPi NEO Plus2: Use regulators for pio
arm64: dts: mediatek: add audio support for mt8365-evk
arm64: dts: mediatek: add afe support for mt8365 SoC
arm64: dts: mediatek: mt8186-corsola: Disable DPI display interface
arm64: dts: mediatek: mt8186: Add svs node
arm64: dts: mediatek: mt8186: Add power domain for DPI
arm64: dts: mediatek: mt8195: Correct clock order for dp_intf*
arm64: dts: mt8183: add dpi node to mt8183
arm64: dts: allwinner: h5: NanoPi Neo Plus2: Fix regulators
arm64: dts: rockchip: add CAN0 and CAN1 interfaces to mecsbc board
arm64: dts: rockchip: add CAN-FD controller nodes to rk3568
arm64: dts: nuvoton: ma35d1: Add uart pinctrl settings
arm64: dts: nuvoton: ma35d1: Add pinctrl and gpio nodes
arm64: dts: nuvoton: Add syscon to the system-management node
ARM: dts: Fix undocumented LM75 compatible nodes
arm64: dts: toshiba: Fix pl011 and pl022 clocks
ARM: dts: stm32: Use SAI to generate bit and frame clock on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Switch bitclock/frame-master to flag on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Sort properties in audio endpoints on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: Add MECIO1 and MECT1S board variants
...
71 lines
1.5 KiB
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71 lines
1.5 KiB
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2021 PHYTEC Messtechnik GmbH
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* Author: Jens Lang <j.lang@phytec.de>
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*
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* Tauri-L RS232 + RS485:
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* - GPIO3_20 uart4_rs485_en needs to be driven high (active)
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* - GPIO3_25 RS485_DE Driver enable
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*/
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#include <dt-bindings/clock/imx8mm-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "imx8mm-pinfunc.h"
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/dts-v1/;
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/plugin/;
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&gpio3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio3_hog>;
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uart4-rs485-en-hog {
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gpio-hog;
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gpios = <20 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "uart4_rs485_en";
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};
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};
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/* UART2 - RS232 */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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assigned-clocks = <&clk IMX8MM_CLK_UART2>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
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status = "okay";
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};
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/* UART4 - RS485 */
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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assigned-clocks = <&clk IMX8MM_CLK_UART4>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
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rts-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;
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linux,rs485-enabled-at-boot-time;
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status = "okay";
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};
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&iomuxc {
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pinctrl_gpio3_hog: gpio3hoggrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00
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MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00
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>;
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};
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
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MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
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MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x49
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>;
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};
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};
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