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946b51882b
Add the device node and related header file for Amlogic A4 reset controller. Signed-off-by: Zelong Dong <zelong.dong@amlogic.com> Link: https://lore.kernel.org/r/20240918074211.8067-3-zelong.dong@amlogic.com Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Kelvin Zhang <kelvin.zhang@amlogic.com> Link: https://lore.kernel.org/r/20250411-a4-a5-reset-v6-2-89963278c686@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
93 lines
2 KiB
C
93 lines
2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __DTS_AMLOGIC_A4_RESET_H
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#define __DTS_AMLOGIC_A4_RESET_H
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/* RESET0 */
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/* 0-3 */
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#define RESET_USB 4
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/* 5-6*/
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#define RESET_U2PHY22 7
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#define RESET_USBPHY20 8
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#define RESET_U2PHY21 9
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#define RESET_USB2DRD 10
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#define RESET_U2H 11
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#define RESET_LED_CTRL 12
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/* 13-31 */
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/* RESET1 */
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#define RESET_AUDIO 32
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#define RESET_AUDIO_VAD 33
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/* 34*/
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#define RESET_DDR_APB 35
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#define RESET_DDR 36
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#define RESET_VOUT_VENC 37
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#define RESET_VOUT 38
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/* 39-47 */
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#define RESET_ETHERNET 48
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/* 49-63 */
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/* RESET2 */
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#define RESET_DEVICE_MMC_ARB 64
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#define RESET_IRCTRL 65
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/* 66*/
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#define RESET_TS_PLL 67
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/* 68-72*/
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#define RESET_SPICC_0 73
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#define RESET_SPICC_1 74
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/* 75-79*/
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#define RESET_MSR_CLK 80
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/* 81*/
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#define RESET_SAR_ADC 82
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/* 83-87*/
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#define RESET_ACODEC 88
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/* 89-90*/
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#define RESET_WATCHDOG 91
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/* 92-95*/
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/* RESET3 */
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/* 96-127 */
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/* RESET4 */
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/* 128-131 */
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#define RESET_PWM_AB 132
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#define RESET_PWM_CD 133
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#define RESET_PWM_EF 134
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#define RESET_PWM_GH 135
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/* 136-137*/
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#define RESET_UART_A 138
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#define RESET_UART_B 139
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/* 140*/
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#define RESET_UART_D 141
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#define RESET_UART_E 142
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/* 143-144*/
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#define RESET_I2C_M_A 145
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#define RESET_I2C_M_B 146
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#define RESET_I2C_M_C 147
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#define RESET_I2C_M_D 148
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/* 149-151*/
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#define RESET_SDEMMC_A 152
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/* 153*/
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#define RESET_SDEMMC_C 154
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/* 155-159*/
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/* RESET5 */
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/* 160-175*/
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#define RESET_BRG_AO_NIC_SYS 176
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/* 177*/
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#define RESET_BRG_AO_NIC_MAIN 178
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#define RESET_BRG_AO_NIC_AUDIO 179
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/* 180-183*/
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#define RESET_BRG_AO_NIC_ALL 184
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/* 185*/
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#define RESET_BRG_NIC_SDIO 186
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#define RESET_BRG_NIC_EMMC 187
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#define RESET_BRG_NIC_DSU 188
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#define RESET_BRG_NIC_CLK81 189
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#define RESET_BRG_NIC_MAIN 190
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#define RESET_BRG_NIC_ALL 191
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#endif
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