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b664f6f7a7
Add a 'thermal-zones' node for stih418. A thermal-zone needs three components: - thermal sensors, described in an earlier commit[1] - cooling devices, specified for each CPU - a thermal zone, describing the overall behavior. The thermal zone needs references to both CPUs and thermal sensors, which phandle are also added. The thermal management will then be achieved on CPUs using the cpufreq framework. [1] https://lore.kernel.org/lkml/20240320-thermal-v3-2-700296694c4a@gmail.com/ Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Raphael Gallais-Pou <rgallaispou@gmail.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
154 lines
4 KiB
Text
154 lines
4 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 STMicroelectronics Limited.
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* Author: Peter Griffin <peter.griffin@linaro.org>
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*/
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#include "stih418-clock.dtsi"
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#include "stih407-family.dtsi"
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#include "stih410-pinctrl.dtsi"
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#include <dt-bindings/thermal/thermal.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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/* u-boot puts hpen in SBC dmem at 0xa4 offset */
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cpu-release-addr = <0x94100A4>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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/* u-boot puts hpen in SBC dmem at 0xa4 offset */
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cpu-release-addr = <0x94100A4>;
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#cooling-cells = <2>;
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};
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};
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usb2_picophy1: phy2 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0xf8 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY0_RESET>;
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reset-names = "global", "port";
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};
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usb2_picophy2: phy3 {
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compatible = "st,stih407-usb2-phy";
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#phy-cells = <0>;
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st,syscfg = <&syscfg_core 0xfc 0xf4>;
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resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
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<&picophyreset STIH407_PICOPHY1_RESET>;
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reset-names = "global", "port";
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <250>; /* 250ms */
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polling-delay = <1000>; /* 1000ms */
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thermal-sensors = <&thermal>;
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trips {
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cpu_crit: cpu-crit {
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temperature = <95000>; /* 95C */
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hysteresis = <2000>;
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type = "critical";
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};
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cpu_alert: cpu-alert {
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temperature = <85000>; /* 85C */
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hysteresis = <2000>;
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type = "passive";
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};
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};
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cooling-maps {
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map {
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trip = <&cpu_alert>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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soc {
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rng11: rng@8a8a000 {
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status = "disabled";
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};
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ohci0: usb@9a03c00 {
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compatible = "st,st-ohci-300x";
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reg = <0x9a03c00 0x100>;
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy1>;
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phy-names = "usb";
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};
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ehci0: usb@9a03e00 {
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compatible = "st,st-ehci-300x";
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reg = <0x9a03e00 0x100>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
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<&softreset STIH407_USB2_PORT0_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy1>;
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phy-names = "usb";
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};
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ohci1: usb@9a83c00 {
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compatible = "st,st-ohci-300x";
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reg = <0x9a83c00 0x100>;
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy2>;
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phy-names = "usb";
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};
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ehci1: usb@9a83e00 {
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compatible = "st,st-ehci-300x";
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reg = <0x9a83e00 0x100>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
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resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
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<&softreset STIH407_USB2_PORT1_SOFTRESET>;
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reset-names = "power", "softreset";
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phys = <&usb2_picophy2>;
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phy-names = "usb";
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};
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mmc0: sdhci@9060000 {
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assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
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assigned-clock-parents = <&clk_s_c0_pll1 0>;
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assigned-clock-rates = <200000000>;
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};
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thermal: thermal@91a0000 {
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compatible = "st,stih407-thermal";
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reg = <0x91a0000 0x28>;
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clock-names = "thermal";
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clocks = <&clk_sysin>;
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interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
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#thermal-sensor-cells = <0>;
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};
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};
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};
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