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38a9dac267
Add basic support for the MediaTek MT6572 SoC. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Max Shevchenko <wctrl@proton.me> Link: https://lore.kernel.org/r/20250702-mt6572-v4-9-bde75b7ed445@proton.me Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
108 lines
2.4 KiB
Text
108 lines
2.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2025 Max Shevchenko <wctrl@proton.me>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&sysirq>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt6589-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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};
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};
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uart_clk: dummy26m {
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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#clock-cells = <0>;
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};
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc_clk: dummy32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt6572-wdt", "mediatek,mt6589-wdt";
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reg = <0x10007000 0x100>;
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interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
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timeout-sec = <15>;
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#reset-cells = <1>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt6572-timer", "mediatek,mt6577-timer";
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reg = <0x10008000 0x80>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&rtc_clk>;
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clock-names = "system-clk", "rtc-clk";
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};
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sysirq: interrupt-controller@10200100 {
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compatible = "mediatek,mt6572-sysirq", "mediatek,mt6577-sysirq";
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reg = <0x10200100 0x1c>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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reg = <0x10211000 0x1000>,
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<0x10212000 0x2000>,
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<0x10214000 0x2000>,
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<0x10216000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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uart0: serial@11005000 {
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compatible = "mediatek,mt6572-uart", "mediatek,mt6577-uart";
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reg = <0x11005000 0x400>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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clock-names = "baud";
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status = "disabled";
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};
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uart1: serial@11006000 {
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compatible = "mediatek,mt6572-uart", "mediatek,mt6577-uart";
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reg = <0x11006000 0x400>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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clock-names = "baud";
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status = "disabled";
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};
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};
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};
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