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724ba67515
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
158 lines
3 KiB
Text
158 lines
3 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2011-2012 Calxeda, Inc.
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*/
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/dts-v1/;
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/* First 4KB has pen for secondary cores. */
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/memreserve/ 0x00000000 0x0001000;
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/ {
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model = "Calxeda Highbank";
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compatible = "calxeda,highbank";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@900 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0x900>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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operating-points = <
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/* kHz ignored */
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1300000 1000000
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1200000 1000000
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1100000 1000000
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800000 1000000
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400000 1000000
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200000 1000000
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>;
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clock-latency = <100000>;
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};
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cpu@901 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0x901>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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operating-points = <
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/* kHz ignored */
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1300000 1000000
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1200000 1000000
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1100000 1000000
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800000 1000000
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400000 1000000
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200000 1000000
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>;
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clock-latency = <100000>;
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};
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cpu@902 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0x902>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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operating-points = <
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/* kHz ignored */
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1300000 1000000
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1200000 1000000
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1100000 1000000
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800000 1000000
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400000 1000000
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200000 1000000
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>;
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clock-latency = <100000>;
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};
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cpu@903 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0x903>;
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next-level-cache = <&L2>;
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clocks = <&a9pll>;
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clock-names = "cpu";
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operating-points = <
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/* kHz ignored */
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1300000 1000000
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1200000 1000000
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1100000 1000000
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800000 1000000
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400000 1000000
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200000 1000000
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>;
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clock-latency = <100000>;
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};
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};
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memory@0 {
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name = "memory";
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device_type = "memory";
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reg = <0x00000000 0xff900000>;
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};
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soc {
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ranges = <0x00000000 0x00000000 0xffffffff>;
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memory-controller@fff00000 {
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compatible = "calxeda,hb-ddr-ctrl";
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reg = <0xfff00000 0x1000>;
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interrupts = <0 91 4>;
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};
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timer@fff10600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xfff10600 0x20>;
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interrupts = <1 13 0xf01>;
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clocks = <&a9periphclk>;
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};
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watchdog@fff10620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0xfff10620 0x20>;
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interrupts = <1 14 0xf01>;
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clocks = <&a9periphclk>;
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};
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intc: interrupt-controller@fff11000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xfff11000 0x1000>,
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<0xfff10100 0x100>;
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};
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xfff12000 0x1000>;
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interrupts = <0 70 4>;
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cache-unified;
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cache-level = <2>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
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};
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sregs@fff3c200 {
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compatible = "calxeda,hb-sregs-l2-ecc";
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reg = <0xfff3c200 0x100>;
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interrupts = <0 71 4>, <0 72 4>;
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};
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};
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};
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/include/ "ecx-common.dtsi"
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