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81f83a36b2
All the BCMBCA SoCs share a set of peripherals at 0xff800000, albeit at slightly varying memory locations on the bus and with varying IRQ assignments. Add the watchdog, GPIO, RNG, LED and DMA blocks for the BCM63178 based on the vendor files 63178_map_part.h and 63178_intr.h from the "bcmopen-consumer" code drop. This SoC has up to 256 possible GPIOs due to having 8 registers with 32 GPIOs in each available. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Link: https://lore.kernel.org/r/20250512-bcmbca-peripherals-arm-v3-8-86f97ab4326f@linaro.org Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
267 lines
5.9 KiB
Text
267 lines
5.9 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Broadcom Ltd.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "brcm,bcm63178", "brcm,bcmbca";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CA7_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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CA7_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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CA7_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
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arm,cpu-registers-not-fw-configured;
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};
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pmu: pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&CA7_0>, <&CA7_1>,
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<&CA7_2>;
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};
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clocks: clocks {
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periph_clk: periph-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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uart_clk: uart-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&periph_clk>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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hsspi_pll: hsspi-pll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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axi@81000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x81000000 0x8000>;
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gic: interrupt-controller@1000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
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reg = <0x1000 0x1000>,
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<0x2000 0x2000>,
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<0x4000 0x2000>,
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<0x6000 0x2000>;
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};
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};
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bus@ff800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xff800000 0x800000>;
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watchdog@480 {
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compatible = "brcm,bcm6345-wdt";
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reg = <0x480 0x10>;
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};
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/* GPIOs 0 .. 31 */
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gpio0: gpio@500 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x500 0x04>, <0x520 0x04>;
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reg-names = "dirout", "dat";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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/* GPIOs 32 .. 63 */
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gpio1: gpio@504 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x504 0x04>, <0x524 0x04>;
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reg-names = "dirout", "dat";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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/* GPIOs 64 .. 95 */
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gpio2: gpio@508 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x508 0x04>, <0x528 0x04>;
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reg-names = "dirout", "dat";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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/* GPIOs 96 .. 127 */
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gpio3: gpio@50c {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x50c 0x04>, <0x52c 0x04>;
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reg-names = "dirout", "dat";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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/* GPIOs 128 .. 159 */
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gpio4: gpio@510 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x510 0x04>, <0x530 0x04>;
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reg-names = "dirout", "dat";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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/* GPIOs 160 .. 191 */
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gpio5: gpio@514 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x514 0x04>, <0x534 0x04>;
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reg-names = "dirout", "dat";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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/* GPIOs 192 .. 223 */
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gpio6: gpio@518 {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x518 0x04>, <0x538 0x04>;
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reg-names = "dirout", "dat";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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/* GPIOs 224 .. 255 */
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gpio7: gpio@51c {
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compatible = "brcm,bcm6345-gpio";
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reg = <0x51c 0x04>, <0x53c 0x04>;
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reg-names = "dirout", "dat";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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rng@b80 {
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compatible = "brcm,iproc-rng200";
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reg = <0xb80 0x28>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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};
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hsspi: spi@1000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0";
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reg = <0x1000 0x600>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&hsspi_pll &hsspi_pll>;
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clock-names = "hsspi", "pll";
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num-cs = <8>;
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status = "disabled";
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};
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nand_controller: nand-controller@1800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
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reg = <0x1800 0x600>, <0x2000 0x10>;
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reg-names = "nand", "nand-int-base";
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status = "disabled";
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nandcs: nand@0 {
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compatible = "brcm,nandcs";
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reg = <0>;
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};
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};
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leds: led-controller@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,bcm63138-leds";
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reg = <0x3000 0xdc>;
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status = "disabled";
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};
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pl081_dma: dma-controller@11000 {
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compatible = "arm,pl081", "arm,primecell";
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// The magic B105F00D info is missing
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arm,primecell-periphid = <0x00041081>;
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reg = <0x11000 0x1000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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memcpy-burst-size = <256>;
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memcpy-bus-width = <32>;
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clocks = <&periph_clk>;
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clock-names = "apb_pclk";
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#dma-cells = <2>;
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};
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uart0: serial@12000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uart_clk>, <&uart_clk>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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};
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};
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