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linux/arch/arm/boot/dts/broadcom/bcm63138.dtsi
Linus Walleij b7907e00f0 ARM: dts: bcm63138: Add BCMBCA peripherals 
All the BCMBCA SoCs share a set of peripherals at 0xff800000,
albeit at slightly varying memory locations on the bus and
with varying IRQ assignments.

Extend the peripheral interrupt window to 0x10000 as it need
to fit the DMA block.

Add the GPIO, RNG and LED and DMA blocks for the
BCM63138 based on the vendor files 63138_map_part.h and
63138_intr.h from the "bcmopen-consumer" code drop.

This SoC has up to 160 possible GPIOs due to having 5
registers with 32 GPIOs in each available.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20250512-bcmbca-peripherals-arm-v3-6-86f97ab4326f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2025-06-09 10:10:40 -07:00

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// SPDX-License-Identifier: GPL-2.0
/*
* Broadcom BCM63138 DSL SoCs Device Tree
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "brcm,bcm63138", "brcm,bcmbca";
model = "Broadcom BCM963138 Reference Board";
interrupt-parent = <&gic>;
aliases {
uart0 = &serial0;
uart1 = &serial1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0>;
enable-method = "brcm,bcm63138";
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <1>;
enable-method = "brcm,bcm63138";
resets = <&pmb0 4 1>;
};
};
clocks {
/* UBUS peripheral clock */
periph_clk: periph_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "periph";
};
/* peripheral clock for system timer */
axi_clk: axi_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&armpll>;
clock-div = <2>;
clock-mult = <1>;
};
/* APB bus clock */
apb_clk: apb_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&armpll>;
clock-div = <4>;
clock-mult = <1>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
};
};
/* ARM bus */
axi@80000000 {
compatible = "simple-bus";
ranges = <0 0x80000000 0x784000>;
#address-cells = <1>;
#size-cells = <1>;
L2: cache-controller@1d000 {
compatible = "arm,pl310-cache";
reg = <0x1d000 0x1000>;
cache-unified;
cache-level = <2>;
cache-size = <524288>;
cache-sets = <1024>;
cache-line-size = <32>;
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
scu: scu@1e000 {
compatible = "arm,cortex-a9-scu";
reg = <0x1e000 0x100>;
};
gic: interrupt-controller@1f000 {
compatible = "arm,cortex-a9-gic";
reg = <0x1f000 0x1000
0x1e100 0x100>;
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
};
global_timer: timer@1e200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x1e200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
clocks = <&axi_clk>;
};
local_timer: local-timer@1e600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1e600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>;
clocks = <&axi_clk>;
};
twd_watchdog: watchdog@1e620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0x1e620 0x20>;
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
armpll: armpll@20000 {
#clock-cells = <0>;
compatible = "brcm,bcm63138-armpll";
clocks = <&periph_clk>;
reg = <0x20000 0xf00>;
};
pmb0: reset-controller@4800c0 {
compatible = "brcm,bcm63138-pmb";
reg = <0x4800c0 0x10>;
#reset-cells = <2>;
};
pmb1: reset-controller@4800e0 {
compatible = "brcm,bcm63138-pmb";
reg = <0x4800e0 0x10>;
#reset-cells = <2>;
};
ahci: sata@a000 {
compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
reg-names = "ahci", "top-ctrl";
reg = <0xa000 0x9ac>, <0x8040 0x24>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&pmb0 3 1>;
reset-names = "ahci";
status = "disabled";
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy0>;
};
};
sata_phy: sata-phy@8100 {
compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
reg = <0x8100 0x1e00>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
};
/* Legacy UBUS base */
ubus@fffe8000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfffe8000 0x10000>;
timer: timer@80 {
compatible = "brcm,bcm6328-timer", "syscon";
reg = <0x80 0x3c>;
};
/* GPIOs 0 .. 31 */
gpio0: gpio@100 {
compatible = "brcm,bcm6345-gpio";
reg = <0x100 0x04>, <0x114 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 32 .. 63 */
gpio1: gpio@104 {
compatible = "brcm,bcm6345-gpio";
reg = <0x104 0x04>, <0x118 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 64 .. 95 */
gpio2: gpio@108 {
compatible = "brcm,bcm6345-gpio";
reg = <0x108 0x04>, <0x11c 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 96 .. 127 */
gpio3: gpio@10c {
compatible = "brcm,bcm6345-gpio";
reg = <0x10c 0x04>, <0x120 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
/* GPIOs 128 .. 159 */
gpio4: gpio@110 {
compatible = "brcm,bcm6345-gpio";
reg = <0x110 0x04>, <0x124 0x04>;
reg-names = "dirout", "dat";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
rng@300 {
compatible = "brcm,iproc-rng200";
reg = <0x300 0x28>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
};
serial0: serial@600 {
compatible = "brcm,bcm6345-uart";
reg = <0x600 0x1b>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "periph";
status = "disabled";
};
serial1: serial@620 {
compatible = "brcm,bcm6345-uart";
reg = <0x620 0x1b>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "periph";
status = "disabled";
};
leds: led-controller@700 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm63138-leds";
reg = <0x700 0xdc>;
status = "disabled";
};
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0";
reg = <0x1000 0x600>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsspi_pll &hsspi_pll>;
clock-names = "hsspi", "pll";
num-cs = <8>;
status = "disabled";
};
nand_controller: nand-controller@2000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
reg = <0x2000 0x600>, <0xf0 0x10>;
reg-names = "nand", "nand-int-base";
status = "disabled";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "nand_ctlrdy";
nandcs: nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
};
};
serial@4400 {
compatible = "brcm,bcm63138-hs-uart", "brcm,bcmbca-hs-uart";
reg = <0x4400 0x1e0>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
bootlut: bootlut@8000 {
compatible = "brcm,bcm63138-bootlut";
reg = <0x8000 0x50>;
};
pl081_dma: dma-controller@d000 {
compatible = "arm,pl081", "arm,primecell";
// The magic B105F00D info is missing
arm,primecell-periphid = <0x00041081>;
reg = <0xd000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
memcpy-burst-size = <256>;
memcpy-bus-width = <32>;
clocks = <&periph_clk>;
clock-names = "apb_pclk";
#dma-cells = <2>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&timer>;
offset = <0x34>;
mask = <1>;
};
};
};
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