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dba600d0f2
Add some crosslinks between pages in the CXL docs - mostly to the ACPI tables. Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-18-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
136 lines
4.2 KiB
ReStructuredText
136 lines
4.2 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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==========================
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One Device per Host Bridge
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==========================
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This system has a single socket with two CXL host bridges. Each host bridge
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has a single CXL memory expander with a 4GB of memory.
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Things to note:
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* Cross-Bridge interleave is not being used.
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* The expanders are in two separate but adjascent memory regions.
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* This CEDT/SRAT describes one node per device
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* The expanders have the same performance and will be in the same memory tier.
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:doc:`CEDT <../acpi/cedt>`::
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Subtable Type : 00 [CXL Host Bridge Structure]
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Reserved : 00
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Length : 0020
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Associated host bridge : 00000007
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Specification version : 00000001
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Reserved : 00000000
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Register base : 0000010370400000
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Register length : 0000000000010000
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Subtable Type : 00 [CXL Host Bridge Structure]
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Reserved : 00
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Length : 0020
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Associated host bridge : 00000006
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Specification version : 00000001
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Reserved : 00000000
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Register base : 0000010380800000
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Register length : 0000000000010000
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Subtable Type : 01 [CXL Fixed Memory Window Structure]
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Reserved : 00
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Length : 002C
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Reserved : 00000000
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Window base address : 0000001000000000
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Window size : 0000000100000000
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Interleave Members (2^n) : 00
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Interleave Arithmetic : 00
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Reserved : 0000
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Granularity : 00000000
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Restrictions : 0006
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QtgId : 0001
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First Target : 00000007
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Subtable Type : 01 [CXL Fixed Memory Window Structure]
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Reserved : 00
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Length : 002C
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Reserved : 00000000
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Window base address : 0000001100000000
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Window size : 0000000100000000
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Interleave Members (2^n) : 00
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Interleave Arithmetic : 00
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Reserved : 0000
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Granularity : 00000000
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Restrictions : 0006
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QtgId : 0001
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First Target : 00000006
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:doc:`SRAT <../acpi/srat>`::
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Subtable Type : 01 [Memory Affinity]
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Length : 28
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Proximity Domain : 00000001
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Reserved1 : 0000
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Base Address : 0000001000000000
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Address Length : 0000000100000000
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Reserved2 : 00000000
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Flags (decoded below) : 0000000B
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Enabled : 1
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Hot Pluggable : 1
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Non-Volatile : 0
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Subtable Type : 01 [Memory Affinity]
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Length : 28
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Proximity Domain : 00000002
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Reserved1 : 0000
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Base Address : 0000001100000000
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Address Length : 0000000100000000
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Reserved2 : 00000000
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Flags (decoded below) : 0000000B
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Enabled : 1
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Hot Pluggable : 1
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Non-Volatile : 0
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:doc:`HMAT <../acpi/hmat>`::
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Structure Type : 0001 [SLLBI]
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Data Type : 00 [Latency]
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Target Proximity Domain List : 00000000
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Target Proximity Domain List : 00000001
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Target Proximity Domain List : 00000002
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Entry : 0080
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Entry : 0100
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Entry : 0100
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Structure Type : 0001 [SLLBI]
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Data Type : 03 [Bandwidth]
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Target Proximity Domain List : 00000000
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Target Proximity Domain List : 00000001
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Target Proximity Domain List : 00000002
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Entry : 1200
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Entry : 0200
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Entry : 0200
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:doc:`SLIT <../acpi/slit>`::
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Signature : "SLIT" [System Locality Information Table]
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Localities : 0000000000000003
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Locality 0 : 10 20 20
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Locality 1 : FF 0A FF
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Locality 2 : FF FF 0A
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:doc:`DSDT <../acpi/dsdt>`::
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Scope (_SB)
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{
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Device (S0D0)
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{
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Name (_HID, "ACPI0016" /* Compute Express Link Host Bridge */) // _HID: Hardware ID
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...
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Name (_UID, 0x07) // _UID: Unique ID
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}
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...
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Device (S0D5)
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{
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Name (_HID, "ACPI0016" /* Compute Express Link Host Bridge */) // _HID: Hardware ID
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...
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Name (_UID, 0x06) // _UID: Unique ID
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}
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}
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