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b663fd4532
Add compatible strings 'nxp,s32g2-lpspi' and 'nxp,s32g3-lpspi' for S32G2 and S32G3. Require nxp,s32g3-lpspi to fallback to nxp,s32g2-lpspi since they are currently compatible. Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-5-6262b9aa9be4@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
103 lines
2.2 KiB
YAML
103 lines
2.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Low Power SPI (LPSPI) for i.MX
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maintainers:
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- Shawn Guo <shawnguo@kernel.org>
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- Sascha Hauer <s.hauer@pengutronix.de>
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- Fabio Estevam <festevam@gmail.com>
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allOf:
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- $ref: /schemas/spi/spi-controller.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,imx7ulp-spi
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- fsl,imx8qxp-spi
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- nxp,s32g2-lpspi
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- items:
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- enum:
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- fsl,imx8ulp-spi
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- fsl,imx93-spi
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- fsl,imx94-spi
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- fsl,imx95-spi
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- const: fsl,imx7ulp-spi
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- items:
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- const: nxp,s32g3-lpspi
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- const: nxp,s32g2-lpspi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: SoC SPI per clock
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- description: SoC SPI ipg clock
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clock-names:
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items:
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- const: per
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- const: ipg
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dmas:
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items:
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- description: TX DMA Channel
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- description: RX DMA Channel
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dma-names:
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items:
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- const: tx
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- const: rx
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fsl,spi-only-use-cs1-sel:
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description:
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spi common code does not support use of CS signals discontinuously.
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i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add
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this property to re-config the chipselect value in the LPSPI driver.
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type: boolean
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num-cs:
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description:
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number of chip selects.
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minimum: 1
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maximum: 2
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default: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx7ulp-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi@40290000 {
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compatible = "fsl,imx7ulp-spi";
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reg = <0x40290000 0x10000>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7ULP_CLK_LPSPI2>,
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<&clks IMX7ULP_CLK_DUMMY>;
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clock-names = "per", "ipg";
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spi-slave;
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fsl,spi-only-use-cs1-sel;
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num-cs = <2>;
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};
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