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30122ce2b9
The driver "drivers/pwm/pwm-imx27.c" never use interrupt. Generally pwm hardware generate a waveform according to register timing setting. Needn't interrupt handle at all. So remove it from "required" list. Signed-off-by: Frank Li <Frank.Li@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240605220839.1398872-1-Frank.Li@nxp.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
86 lines
1.8 KiB
YAML
86 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX PWM controller
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maintainers:
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- Philipp Zabel <p.zabel@pengutronix.de>
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allOf:
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- $ref: pwm.yaml#
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properties:
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"#pwm-cells":
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description:
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The only third cell flag supported by this binding is
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PWM_POLARITY_INVERTED. fsl,imx1-pwm does not support this flags.
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const: 3
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compatible:
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oneOf:
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- enum:
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- fsl,imx1-pwm
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- fsl,imx27-pwm
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- items:
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- enum:
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- fsl,imx25-pwm
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- fsl,imx31-pwm
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- fsl,imx50-pwm
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- fsl,imx51-pwm
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- fsl,imx53-pwm
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- fsl,imx6q-pwm
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- fsl,imx6sl-pwm
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- fsl,imx6sll-pwm
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- fsl,imx6sx-pwm
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- fsl,imx6ul-pwm
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- fsl,imx7d-pwm
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- fsl,imx8mm-pwm
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- fsl,imx8mn-pwm
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- fsl,imx8mp-pwm
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- fsl,imx8mq-pwm
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- fsl,imx8qxp-pwm
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- const: fsl,imx27-pwm
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reg:
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maxItems: 1
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clocks:
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items:
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- description: SoC PWM ipg clock
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- description: SoC PWM per clock
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clock-names:
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items:
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- const: ipg
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- const: per
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx5-clock.h>
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pwm@53fb4000 {
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#pwm-cells = <3>;
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compatible = "fsl,imx27-pwm";
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reg = <0x53fb4000 0x4000>;
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clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
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<&clks IMX5_CLK_PWM1_HF_GATE>;
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clock-names = "ipg", "per";
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interrupts = <61>;
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};
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