linux/Documentation/devicetree/bindings/memory-controllers/qca,ath79-ddr-controller.yaml
Rob Herring (Arm) 92c58adcee dt-bindings: memory-controller: qca,ath79-ddr-controller: Drop consumer from example
Normal practice is examples only show what the binding document defines
and doesn't include consumers in a provider example (or vice-versa). The
"qca,ddr-wb-channel-interrupts" and "qca,ddr-wb-channels" properties are
also not yet documented by a schema, so avoid (not yet enabled) warnings
on them by dropping the interrupt-controller node from the example.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20250103212448.2852884-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-01-07 08:35:34 -06:00

54 lines
1.4 KiB
YAML

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
The DDR controller of the AR7xxx and AR9xxx families provides an interface to
flush the FIFO between various devices and the DDR. This is mainly used by
the IRQ controller to flush the FIFO before running the interrupt handler of
such devices.
properties:
compatible:
oneOf:
- items:
- const: qca,ar9132-ddr-controller
- const: qca,ar7240-ddr-controller
- items:
- enum:
- qca,ar7100-ddr-controller
- qca,ar7240-ddr-controller
"#qca,ddr-wb-channel-cells":
description: |
Specifies the number of cells needed to encode the write buffer channel
index.
$ref: /schemas/types.yaml#/definitions/uint32
const: 1
reg:
maxItems: 1
required:
- compatible
- "#qca,ddr-wb-channel-cells"
- reg
additionalProperties: false
examples:
- |
ddr_ctrl: memory-controller@18000000 {
compatible = "qca,ar9132-ddr-controller",
"qca,ar7240-ddr-controller";
reg = <0x18000000 0x100>;
#qca,ddr-wb-channel-cells = <1>;
};