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f3ce2e12a2
Convert the Qualcomm Atheros ath79 CPU interrupt controller binding to schema format. Link: https://lore.kernel.org/r/20250505144817.1291980-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
61 lines
1.6 KiB
YAML
61 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/qca,ar7100-cpu-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Atheros ath79 CPU interrupt controller
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maintainers:
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- Alban Bedel <albeu@free.fr>
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description:
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On most SoC the IRQ controller need to flush the DDR FIFO before running the
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interrupt handler of some devices. This is configured using the
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qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
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properties:
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compatible:
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oneOf:
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- items:
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- const: qca,ar9132-cpu-intc
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- const: qca,ar7100-cpu-intc
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- items:
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- const: qca,ar7100-cpu-intc
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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qca,ddr-wb-channel-interrupts:
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description: List of interrupts needing a write buffer flush
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$ref: /schemas/types.yaml#/definitions/uint32-array
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qca,ddr-wb-channels:
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description: List of write buffer channel phandles for each interrupt
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$ref: /schemas/types.yaml#/definitions/phandle-array
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required:
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- compatible
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- interrupt-controller
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- '#interrupt-cells'
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additionalProperties: false
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examples:
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- |
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interrupt-controller {
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compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
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qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
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<&ddr_ctrl 0>, <&ddr_ctrl 1>;
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};
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ddr_ctrl: memory-controller {
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#qca,ddr-wb-channel-cells = <1>;
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};
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