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4c4ade1aba
Add another batch of various "simple" syscon compatibles which were undocumented or still documented with old text bindings. Remove the old text binding docs for the ones which were documented. Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> # mtd Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240603131230.136196-2-robh@kernel.org Signed-off-by: Lee Jones <lee@kernel.org>
70 lines
1.4 KiB
Text
70 lines
1.4 KiB
Text
========================================================
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Secondary CPU enable-method "al,alpine-smp" binding
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========================================================
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This document describes the "al,alpine-smp" method for
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enabling secondary CPUs. To apply to all CPUs, a single
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"al,alpine-smp" enable method should be defined in the
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"cpus" node.
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Enable method name: "al,alpine-smp"
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Compatible machines: "al,alpine"
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Compatible CPUs: "arm,cortex-a15"
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Related properties: (none)
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Note:
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This enable method requires valid nodes compatible with
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"al,alpine-cpu-resume" and "al,alpine-nb-service".
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* Alpine CPU resume registers
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The CPU resume register are used to define required resume address after
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reset.
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Properties:
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- compatible : Should contain "al,alpine-cpu-resume".
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- reg : Offset and length of the register set for the device
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Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "al,alpine-smp";
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cpu@0 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <3>;
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};
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};
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cpu_resume {
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compatible = "al,alpine-cpu-resume";
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reg = <0xfbff5ed0 0x30>;
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};
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nb_service {
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compatible = "al,alpine-sysfabric-service", "syscon";
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reg = <0xfb070000 0x10000>;
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};
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