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Some NVIDIA PMUs like the NVLINK-C2C, CNVLINK, and PCIE PMU provide port filtering. If the port filter is set to zero, the counter of these PMUs will not capture any event. To avoid meaningless experiment, the driver sets the port filter value to a default non-zero value. Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Link: https://lore.kernel.org/r/20241031142118.1865965-5-bwicaksono@nvidia.com Signed-off-by: Will Deacon <will@kernel.org>
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333 lines
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=========================================================
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NVIDIA Tegra SoC Uncore Performance Monitoring Unit (PMU)
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=========================================================
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The NVIDIA Tegra SoC includes various system PMUs to measure key performance
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metrics like memory bandwidth, latency, and utilization:
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* Scalable Coherency Fabric (SCF)
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* NVLink-C2C0
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* NVLink-C2C1
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* CNVLink
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* PCIE
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PMU Driver
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----------
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The PMUs in this document are based on ARM CoreSight PMU Architecture as
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described in document: ARM IHI 0091. Since this is a standard architecture, the
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PMUs are managed by a common driver "arm-cs-arch-pmu". This driver describes
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the available events and configuration of each PMU in sysfs. Please see the
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sections below to get the sysfs path of each PMU. Like other uncore PMU drivers,
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the driver provides "cpumask" sysfs attribute to show the CPU id used to handle
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the PMU event. There is also "associated_cpus" sysfs attribute, which contains a
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list of CPUs associated with the PMU instance.
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.. _SCF_PMU_Section:
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SCF PMU
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-------
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The SCF PMU monitors system level cache events, CPU traffic, and
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strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
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:ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about the PMU
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traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_source/devices/nvidia_scf_pmu_<socket-id>.
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Example usage:
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* Count event id 0x0 in socket 0::
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perf stat -a -e nvidia_scf_pmu_0/event=0x0/
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* Count event id 0x0 in socket 1::
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perf stat -a -e nvidia_scf_pmu_1/event=0x0/
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NVLink-C2C0 PMU
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--------------------
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The NVLink-C2C0 PMU monitors incoming traffic from a GPU/CPU connected with
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NVLink-C2C (Chip-2-Chip) interconnect. The type of traffic captured by this PMU
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varies dependent on the chip configuration:
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* NVIDIA Grace Hopper Superchip: Hopper GPU is connected with Grace SoC.
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In this config, the PMU captures GPU ATS translated or EGM traffic from the GPU.
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* NVIDIA Grace CPU Superchip: two Grace CPU SoCs are connected.
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In this config, the PMU captures read and relaxed ordered (RO) writes from
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PCIE device of the remote SoC.
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Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about
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the PMU traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_source/devices/nvidia_nvlink_c2c0_pmu_<socket-id>.
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Example usage:
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* Count event id 0x0 from the GPU/CPU connected with socket 0::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0/
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* Count event id 0x0 from the GPU/CPU connected with socket 1::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_1/event=0x0/
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* Count event id 0x0 from the GPU/CPU connected with socket 2::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_2/event=0x0/
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* Count event id 0x0 from the GPU/CPU connected with socket 3::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_3/event=0x0/
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The NVLink-C2C has two ports that can be connected to one GPU (occupying both
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ports) or to two GPUs (one GPU per port). The user can use "port" bitmap
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parameter to select the port(s) to monitor. Each bit represents the port number,
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e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The
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PMU will monitor both ports by default if not specified.
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Example for port filtering:
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* Count event id 0x0 from the GPU connected with socket 0 on port 0::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x1/
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* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1::
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perf stat -a -e nvidia_nvlink_c2c0_pmu_0/event=0x0,port=0x3/
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NVLink-C2C1 PMU
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-------------------
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The NVLink-C2C1 PMU monitors incoming traffic from a GPU connected with
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NVLink-C2C (Chip-2-Chip) interconnect. This PMU captures untranslated GPU
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traffic, in contrast with NvLink-C2C0 PMU that captures ATS translated traffic.
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Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about
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the PMU traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_source/devices/nvidia_nvlink_c2c1_pmu_<socket-id>.
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Example usage:
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* Count event id 0x0 from the GPU connected with socket 0::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0/
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* Count event id 0x0 from the GPU connected with socket 1::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_1/event=0x0/
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* Count event id 0x0 from the GPU connected with socket 2::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_2/event=0x0/
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* Count event id 0x0 from the GPU connected with socket 3::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_3/event=0x0/
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The NVLink-C2C has two ports that can be connected to one GPU (occupying both
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ports) or to two GPUs (one GPU per port). The user can use "port" bitmap
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parameter to select the port(s) to monitor. Each bit represents the port number,
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e.g. "port=0x1" corresponds to port 0 and "port=0x3" is for port 0 and 1. The
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PMU will monitor both ports by default if not specified.
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Example for port filtering:
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* Count event id 0x0 from the GPU connected with socket 0 on port 0::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x1/
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* Count event id 0x0 from the GPUs connected with socket 0 on port 0 and port 1::
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perf stat -a -e nvidia_nvlink_c2c1_pmu_0/event=0x0,port=0x3/
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CNVLink PMU
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---------------
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The CNVLink PMU monitors traffic from GPU and PCIE device on remote sockets
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to local memory. For PCIE traffic, this PMU captures read and relaxed ordered
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(RO) write traffic. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`
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for more info about the PMU traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>.
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Each SoC socket can be connected to one or more sockets via CNVLink. The user can
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use "rem_socket" bitmap parameter to select the remote socket(s) to monitor.
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Each bit represents the socket number, e.g. "rem_socket=0xE" corresponds to
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socket 1 to 3. The PMU will monitor all remote sockets by default if not
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specified.
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/sys/bus/event_source/devices/nvidia_cnvlink_pmu_<socket-id>/format/rem_socket
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shows the valid bits that can be set in the "rem_socket" parameter.
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The PMU can not distinguish the remote traffic initiator, therefore it does not
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provide filter to select the traffic source to monitor. It reports combined
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traffic from remote GPU and PCIE devices.
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Example usage:
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* Count event id 0x0 for the traffic from remote socket 1, 2, and 3 to socket 0::
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perf stat -a -e nvidia_cnvlink_pmu_0/event=0x0,rem_socket=0xE/
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* Count event id 0x0 for the traffic from remote socket 0, 2, and 3 to socket 1::
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perf stat -a -e nvidia_cnvlink_pmu_1/event=0x0,rem_socket=0xD/
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* Count event id 0x0 for the traffic from remote socket 0, 1, and 3 to socket 2::
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perf stat -a -e nvidia_cnvlink_pmu_2/event=0x0,rem_socket=0xB/
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* Count event id 0x0 for the traffic from remote socket 0, 1, and 2 to socket 3::
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perf stat -a -e nvidia_cnvlink_pmu_3/event=0x0,rem_socket=0x7/
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PCIE PMU
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------------
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The PCIE PMU monitors all read/write traffic from PCIE root ports to
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local/remote memory. Please see :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section`
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for more info about the PMU traffic coverage.
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The events and configuration options of this PMU device are described in sysfs,
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see /sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>.
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Each SoC socket can support multiple root ports. The user can use
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"root_port" bitmap parameter to select the port(s) to monitor, i.e.
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"root_port=0xF" corresponds to root port 0 to 3. The PMU will monitor all root
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ports by default if not specified.
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/sys/bus/event_source/devices/nvidia_pcie_pmu_<socket-id>/format/root_port
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shows the valid bits that can be set in the "root_port" parameter.
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Example usage:
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* Count event id 0x0 from root port 0 and 1 of socket 0::
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perf stat -a -e nvidia_pcie_pmu_0/event=0x0,root_port=0x3/
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* Count event id 0x0 from root port 0 and 1 of socket 1::
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perf stat -a -e nvidia_pcie_pmu_1/event=0x0,root_port=0x3/
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.. _NVIDIA_Uncore_PMU_Traffic_Coverage_Section:
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Traffic Coverage
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----------------
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The PMU traffic coverage may vary dependent on the chip configuration:
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* **NVIDIA Grace Hopper Superchip**: Hopper GPU is connected with Grace SoC.
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Example configuration with two Grace SoCs::
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********************************* *********************************
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* SOCKET-A * * SOCKET-B *
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* * * *
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* :::::::: * * :::::::: *
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* : PCIE : * * : PCIE : *
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* :::::::: * * :::::::: *
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* | * * | *
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* | * * | *
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* ::::::: ::::::::: * * ::::::::: ::::::: *
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* : : : : * * : : : : *
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* : GPU :<--NVLink-->: Grace :<---CNVLink--->: Grace :<--NVLink-->: GPU : *
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* : : C2C : SoC : * * : SoC : C2C : : *
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* ::::::: ::::::::: * * ::::::::: ::::::: *
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* | | * * | | *
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* | | * * | | *
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* &&&&&&&& &&&&&&&& * * &&&&&&&& &&&&&&&& *
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* & GMEM & & CMEM & * * & CMEM & & GMEM & *
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* &&&&&&&& &&&&&&&& * * &&&&&&&& &&&&&&&& *
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* * * *
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********************************* *********************************
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GMEM = GPU Memory (e.g. HBM)
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CMEM = CPU Memory (e.g. LPDDR5X)
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| Following table contains traffic coverage of Grace SoC PMU in socket-A:
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::
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+--------------+-------+-----------+-----------+-----+----------+----------+
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| | Source |
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+ +-------+-----------+-----------+-----+----------+----------+
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| Destination | |GPU ATS |GPU Not-ATS| | Socket-B | Socket-B |
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| |PCI R/W|Translated,|Translated | CPU | CPU/PCIE1| GPU/PCIE2|
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| | |EGM | | | | |
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+==============+=======+===========+===========+=====+==========+==========+
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| Local | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | SCF PMU | CNVLink |
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| SYSRAM/CMEM | PMU |PMU |PMU | PMU | | PMU |
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+--------------+-------+-----------+-----------+-----+----------+----------+
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| Local GMEM | PCIE | N/A |NVLink-C2C1| SCF | SCF PMU | CNVLink |
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| | PMU | |PMU | PMU | | PMU |
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+--------------+-------+-----------+-----------+-----+----------+----------+
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| Remote | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | | |
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| SYSRAM/CMEM | PMU |PMU |PMU | PMU | N/A | N/A |
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| over CNVLink | | | | | | |
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+--------------+-------+-----------+-----------+-----+----------+----------+
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| Remote GMEM | PCIE |NVLink-C2C0|NVLink-C2C1| SCF | | |
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| over CNVLink | PMU |PMU |PMU | PMU | N/A | N/A |
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+--------------+-------+-----------+-----------+-----+----------+----------+
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PCIE1 traffic represents strongly ordered (SO) writes.
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PCIE2 traffic represents reads and relaxed ordered (RO) writes.
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* **NVIDIA Grace CPU Superchip**: two Grace CPU SoCs are connected.
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Example configuration with two Grace SoCs::
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******************* *******************
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* SOCKET-A * * SOCKET-B *
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* * * *
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* :::::::: * * :::::::: *
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* : PCIE : * * : PCIE : *
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* :::::::: * * :::::::: *
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* | * * | *
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* | * * | *
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* ::::::::: * * ::::::::: *
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* : : * * : : *
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* : Grace :<--------NVLink------->: Grace : *
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* : SoC : * C2C * : SoC : *
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* ::::::::: * * ::::::::: *
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* | * * | *
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* | * * | *
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* &&&&&&&& * * &&&&&&&& *
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* & CMEM & * * & CMEM & *
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* &&&&&&&& * * &&&&&&&& *
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* * * *
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******************* *******************
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GMEM = GPU Memory (e.g. HBM)
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CMEM = CPU Memory (e.g. LPDDR5X)
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| Following table contains traffic coverage of Grace SoC PMU in socket-A:
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::
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+-----------------+-----------+---------+----------+-------------+
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| | Source |
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+ +-----------+---------+----------+-------------+
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| Destination | | | Socket-B | Socket-B |
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| | PCI R/W | CPU | CPU/PCIE1| PCIE2 |
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| | | | | |
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+=================+===========+=========+==========+=============+
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| Local | PCIE PMU | SCF PMU | SCF PMU | NVLink-C2C0 |
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| SYSRAM/CMEM | | | | PMU |
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+-----------------+-----------+---------+----------+-------------+
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| Remote | | | | |
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| SYSRAM/CMEM | PCIE PMU | SCF PMU | N/A | N/A |
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| over NVLink-C2C | | | | |
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+-----------------+-----------+---------+----------+-------------+
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PCIE1 traffic represents strongly ordered (SO) writes.
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PCIE2 traffic represents reads and relaxed ordered (RO) writes.
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