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afec1aba08
Document the device tree bindings for the Renesas RZ/V2H(P) SoC Clock Pulse Generator (CPG). CPG block handles the below operations: - Generation and control of clock signals for the IP modules - Generation and control of resets - Control over booting - Low power consumption and power supply domains Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the core clocks are a subset of the ones which are listed as part of section 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240729202645.263525-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
21 lines
681 B
C
21 lines
681 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
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#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* Core Clock list */
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#define R9A09G057_SYS_0_PCLK 0
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#define R9A09G057_CA55_0_CORE_CLK0 1
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#define R9A09G057_CA55_0_CORE_CLK1 2
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#define R9A09G057_CA55_0_CORE_CLK2 3
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#define R9A09G057_CA55_0_CORE_CLK3 4
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#define R9A09G057_CA55_0_PERIPHCLK 5
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#define R9A09G057_CM33_CLK0 6
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#define R9A09G057_CST_0_SWCLKTCK 7
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#define R9A09G057_IOTOP_0_SHCLK 8
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#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */
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