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Currently, we enable cbo.zero for usermode on each hart that supports the Zicboz extension. This means that the [ms]envcfg CSR value may differ between harts. Other features, such as pointer masking and CFI, require setting [ms]envcfg bits on a per-thread basis. The combination of these two adds quite some complexity and overhead to context switching, as we would need to maintain two separate masks for the per-hart and per-thread bits. Andrew Jones, who originally added Zicboz support, writes[1][2]: I've approached Zicboz the same way I would approach all extensions, which is to be per-hart. I'm not currently aware of a platform that is / will be composed of harts where some have Zicboz and others don't, but there's nothing stopping a platform like that from being built. So, how about we add code that confirms Zicboz is on all harts. If any hart does not have it, then we complain loudly and disable it on all the other harts. If it was just a hardware description bug, then it'll get fixed. If there's actually a platform which doesn't have Zicboz on all harts, then, when the issue is reported, we can decide to not support it, support it with defconfig, or support it under a Kconfig guard which must be enabled by the user. Let's follow his suggested solution and require the extension to be available on all harts, so the envcfg CSR value does not need to change when a thread migrates between harts. Since we are doing this for all extensions with fields in envcfg, the CSR itself only needs to be saved/ restored when it is present on all harts. This should not be a regression as no known hardware has asymmetric Zicboz support, but if anyone reports seeing the warning, we will re-evaluate our solution. Link: https://lore.kernel.org/linux-riscv/20240322-168f191eeb8479b2ea169a5e@orel/ [1] Link: https://lore.kernel.org/linux-riscv/20240323-28943722feb57a41fb0ff488@orel/ [2] Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Deepak Gupta <debug@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> Link: https://lore.kernel.org/r/20240814081126.956287-2-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
183 lines
4.4 KiB
C
183 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*/
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#define pr_fmt(fmt) "suspend: " fmt
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#include <linux/ftrace.h>
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#include <linux/suspend.h>
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#include <asm/csr.h>
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#include <asm/sbi.h>
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#include <asm/suspend.h>
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void suspend_save_csrs(struct suspend_context *context)
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{
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if (riscv_has_extension_unlikely(RISCV_ISA_EXT_XLINUXENVCFG))
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context->envcfg = csr_read(CSR_ENVCFG);
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context->tvec = csr_read(CSR_TVEC);
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context->ie = csr_read(CSR_IE);
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/*
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* No need to save/restore IP CSR (i.e. MIP or SIP) because:
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*
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* 1. For no-MMU (M-mode) kernel, the bits in MIP are set by
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* external devices (such as interrupt controller, timer, etc).
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* 2. For MMU (S-mode) kernel, the bits in SIP are set by
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* M-mode firmware and external devices (such as interrupt
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* controller, etc).
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*/
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#ifdef CONFIG_MMU
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context->satp = csr_read(CSR_SATP);
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#endif
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}
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void suspend_restore_csrs(struct suspend_context *context)
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{
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csr_write(CSR_SCRATCH, 0);
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if (riscv_has_extension_unlikely(RISCV_ISA_EXT_XLINUXENVCFG))
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csr_write(CSR_ENVCFG, context->envcfg);
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csr_write(CSR_TVEC, context->tvec);
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csr_write(CSR_IE, context->ie);
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#ifdef CONFIG_MMU
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csr_write(CSR_SATP, context->satp);
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#endif
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}
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int cpu_suspend(unsigned long arg,
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int (*finish)(unsigned long arg,
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unsigned long entry,
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unsigned long context))
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{
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int rc = 0;
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struct suspend_context context = { 0 };
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/* Finisher should be non-NULL */
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if (!finish)
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return -EINVAL;
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/* Save additional CSRs*/
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suspend_save_csrs(&context);
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/*
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* Function graph tracer state gets incosistent when the kernel
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* calls functions that never return (aka finishers) hence disable
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* graph tracing during their execution.
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*/
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pause_graph_tracing();
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/* Save context on stack */
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if (__cpu_suspend_enter(&context)) {
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/* Call the finisher */
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rc = finish(arg, __pa_symbol(__cpu_resume_enter),
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(ulong)&context);
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/*
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* Should never reach here, unless the suspend finisher
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* fails. Successful cpu_suspend() should return from
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* __cpu_resume_entry()
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*/
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if (!rc)
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rc = -EOPNOTSUPP;
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}
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/* Enable function graph tracer */
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unpause_graph_tracing();
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/* Restore additional CSRs */
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suspend_restore_csrs(&context);
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return rc;
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}
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#ifdef CONFIG_RISCV_SBI
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static int sbi_system_suspend(unsigned long sleep_type,
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unsigned long resume_addr,
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unsigned long opaque)
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{
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struct sbiret ret;
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ret = sbi_ecall(SBI_EXT_SUSP, SBI_EXT_SUSP_SYSTEM_SUSPEND,
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sleep_type, resume_addr, opaque, 0, 0, 0);
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if (ret.error)
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return sbi_err_map_linux_errno(ret.error);
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return ret.value;
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}
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static int sbi_system_suspend_enter(suspend_state_t state)
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{
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return cpu_suspend(SBI_SUSP_SLEEP_TYPE_SUSPEND_TO_RAM, sbi_system_suspend);
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}
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static const struct platform_suspend_ops sbi_system_suspend_ops = {
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.valid = suspend_valid_only_mem,
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.enter = sbi_system_suspend_enter,
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};
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static int __init sbi_system_suspend_init(void)
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{
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if (sbi_spec_version >= sbi_mk_version(2, 0) &&
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sbi_probe_extension(SBI_EXT_SUSP) > 0) {
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pr_info("SBI SUSP extension detected\n");
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if (IS_ENABLED(CONFIG_SUSPEND))
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suspend_set_ops(&sbi_system_suspend_ops);
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}
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return 0;
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}
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arch_initcall(sbi_system_suspend_init);
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static int sbi_suspend_finisher(unsigned long suspend_type,
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unsigned long resume_addr,
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unsigned long opaque)
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{
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struct sbiret ret;
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ret = sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_SUSPEND,
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suspend_type, resume_addr, opaque, 0, 0, 0);
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return (ret.error) ? sbi_err_map_linux_errno(ret.error) : 0;
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}
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int riscv_sbi_hart_suspend(u32 state)
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{
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if (state & SBI_HSM_SUSP_NON_RET_BIT)
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return cpu_suspend(state, sbi_suspend_finisher);
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else
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return sbi_suspend_finisher(state, 0, 0);
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}
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bool riscv_sbi_suspend_state_is_valid(u32 state)
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{
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if (state > SBI_HSM_SUSPEND_RET_DEFAULT &&
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state < SBI_HSM_SUSPEND_RET_PLATFORM)
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return false;
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if (state > SBI_HSM_SUSPEND_NON_RET_DEFAULT &&
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state < SBI_HSM_SUSPEND_NON_RET_PLATFORM)
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return false;
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return true;
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}
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bool riscv_sbi_hsm_is_supported(void)
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{
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/*
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* The SBI HSM suspend function is only available when:
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* 1) SBI version is 0.3 or higher
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* 2) SBI HSM extension is available
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*/
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if (sbi_spec_version < sbi_mk_version(0, 3) ||
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!sbi_probe_extension(SBI_EXT_HSM)) {
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pr_info("HSM suspend not available\n");
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return false;
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}
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return true;
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}
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#endif /* CONFIG_RISCV_SBI */
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