mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
fc58db9aeb
Platform firmware event data field is allowed to be 62 bits for
Linux as uppper most two bits are reserved to indicate SBI fw or
platform specific firmware events.
However, the event data field is masked as per the hardware raw
event mask which is not correct.
Fix the platform firmware event data field with proper mask.
Fixes: f0c9363db2 ("perf/riscv-sbi: Add platform specific firmware event handling")
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241212-pmu_event_fixes_v2-v2-1-813e8a4f5962@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
543 lines
16 KiB
C
543 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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* Copyright (c) 2020 Western Digital Corporation or its affiliates.
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*/
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#ifndef _ASM_RISCV_SBI_H
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#define _ASM_RISCV_SBI_H
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#include <linux/types.h>
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#include <linux/cpumask.h>
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#include <linux/jump_label.h>
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#ifdef CONFIG_RISCV_SBI
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enum sbi_ext_id {
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#ifdef CONFIG_RISCV_SBI_V01
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SBI_EXT_0_1_SET_TIMER = 0x0,
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SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
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SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
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SBI_EXT_0_1_CLEAR_IPI = 0x3,
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SBI_EXT_0_1_SEND_IPI = 0x4,
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SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
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SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
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SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
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SBI_EXT_0_1_SHUTDOWN = 0x8,
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#endif
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SBI_EXT_BASE = 0x10,
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SBI_EXT_TIME = 0x54494D45,
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SBI_EXT_IPI = 0x735049,
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SBI_EXT_RFENCE = 0x52464E43,
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SBI_EXT_HSM = 0x48534D,
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SBI_EXT_SRST = 0x53525354,
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SBI_EXT_SUSP = 0x53555350,
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SBI_EXT_PMU = 0x504D55,
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SBI_EXT_DBCN = 0x4442434E,
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SBI_EXT_STA = 0x535441,
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SBI_EXT_NACL = 0x4E41434C,
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/* Experimentals extensions must lie within this range */
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SBI_EXT_EXPERIMENTAL_START = 0x08000000,
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SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF,
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/* Vendor extensions must lie within this range */
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SBI_EXT_VENDOR_START = 0x09000000,
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SBI_EXT_VENDOR_END = 0x09FFFFFF,
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};
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enum sbi_ext_base_fid {
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SBI_EXT_BASE_GET_SPEC_VERSION = 0,
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SBI_EXT_BASE_GET_IMP_ID,
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SBI_EXT_BASE_GET_IMP_VERSION,
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SBI_EXT_BASE_PROBE_EXT,
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SBI_EXT_BASE_GET_MVENDORID,
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SBI_EXT_BASE_GET_MARCHID,
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SBI_EXT_BASE_GET_MIMPID,
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};
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enum sbi_ext_time_fid {
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SBI_EXT_TIME_SET_TIMER = 0,
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};
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enum sbi_ext_ipi_fid {
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SBI_EXT_IPI_SEND_IPI = 0,
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};
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enum sbi_ext_rfence_fid {
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SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
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SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
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SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
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SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
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SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
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SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
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SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
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};
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enum sbi_ext_hsm_fid {
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SBI_EXT_HSM_HART_START = 0,
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SBI_EXT_HSM_HART_STOP,
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SBI_EXT_HSM_HART_STATUS,
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SBI_EXT_HSM_HART_SUSPEND,
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};
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enum sbi_hsm_hart_state {
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SBI_HSM_STATE_STARTED = 0,
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SBI_HSM_STATE_STOPPED,
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SBI_HSM_STATE_START_PENDING,
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SBI_HSM_STATE_STOP_PENDING,
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SBI_HSM_STATE_SUSPENDED,
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SBI_HSM_STATE_SUSPEND_PENDING,
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SBI_HSM_STATE_RESUME_PENDING,
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};
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#define SBI_HSM_SUSP_BASE_MASK 0x7fffffff
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#define SBI_HSM_SUSP_NON_RET_BIT 0x80000000
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#define SBI_HSM_SUSP_PLAT_BASE 0x10000000
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#define SBI_HSM_SUSPEND_RET_DEFAULT 0x00000000
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#define SBI_HSM_SUSPEND_RET_PLATFORM SBI_HSM_SUSP_PLAT_BASE
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#define SBI_HSM_SUSPEND_RET_LAST SBI_HSM_SUSP_BASE_MASK
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#define SBI_HSM_SUSPEND_NON_RET_DEFAULT SBI_HSM_SUSP_NON_RET_BIT
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#define SBI_HSM_SUSPEND_NON_RET_PLATFORM (SBI_HSM_SUSP_NON_RET_BIT | \
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SBI_HSM_SUSP_PLAT_BASE)
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#define SBI_HSM_SUSPEND_NON_RET_LAST (SBI_HSM_SUSP_NON_RET_BIT | \
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SBI_HSM_SUSP_BASE_MASK)
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enum sbi_ext_srst_fid {
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SBI_EXT_SRST_RESET = 0,
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};
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enum sbi_srst_reset_type {
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SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
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SBI_SRST_RESET_TYPE_COLD_REBOOT,
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SBI_SRST_RESET_TYPE_WARM_REBOOT,
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};
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enum sbi_srst_reset_reason {
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SBI_SRST_RESET_REASON_NONE = 0,
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SBI_SRST_RESET_REASON_SYS_FAILURE,
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};
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enum sbi_ext_susp_fid {
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SBI_EXT_SUSP_SYSTEM_SUSPEND = 0,
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};
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enum sbi_ext_susp_sleep_type {
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SBI_SUSP_SLEEP_TYPE_SUSPEND_TO_RAM = 0,
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};
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enum sbi_ext_pmu_fid {
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SBI_EXT_PMU_NUM_COUNTERS = 0,
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SBI_EXT_PMU_COUNTER_GET_INFO,
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SBI_EXT_PMU_COUNTER_CFG_MATCH,
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SBI_EXT_PMU_COUNTER_START,
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SBI_EXT_PMU_COUNTER_STOP,
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SBI_EXT_PMU_COUNTER_FW_READ,
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SBI_EXT_PMU_COUNTER_FW_READ_HI,
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SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
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};
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union sbi_pmu_ctr_info {
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unsigned long value;
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struct {
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unsigned long csr:12;
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unsigned long width:6;
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#if __riscv_xlen == 32
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unsigned long reserved:13;
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#else
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unsigned long reserved:45;
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#endif
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unsigned long type:1;
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};
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};
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/* Data structure to contain the pmu snapshot data */
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struct riscv_pmu_snapshot_data {
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u64 ctr_overflow_mask;
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u64 ctr_values[64];
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u64 reserved[447];
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};
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#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)
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#define RISCV_PMU_PLAT_FW_EVENT_MASK GENMASK_ULL(61, 0)
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#define RISCV_PMU_RAW_EVENT_IDX 0x20000
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#define RISCV_PLAT_FW_EVENT 0xFFFF
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/** General pmu event codes specified in SBI PMU extension */
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enum sbi_pmu_hw_generic_events_t {
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SBI_PMU_HW_NO_EVENT = 0,
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SBI_PMU_HW_CPU_CYCLES = 1,
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SBI_PMU_HW_INSTRUCTIONS = 2,
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SBI_PMU_HW_CACHE_REFERENCES = 3,
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SBI_PMU_HW_CACHE_MISSES = 4,
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SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5,
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SBI_PMU_HW_BRANCH_MISSES = 6,
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SBI_PMU_HW_BUS_CYCLES = 7,
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SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8,
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SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9,
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SBI_PMU_HW_REF_CPU_CYCLES = 10,
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SBI_PMU_HW_GENERAL_MAX,
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};
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/**
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* Special "firmware" events provided by the firmware, even if the hardware
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* does not support performance events. These events are encoded as a raw
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* event type in Linux kernel perf framework.
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*/
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enum sbi_pmu_fw_generic_events_t {
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SBI_PMU_FW_MISALIGNED_LOAD = 0,
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SBI_PMU_FW_MISALIGNED_STORE = 1,
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SBI_PMU_FW_ACCESS_LOAD = 2,
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SBI_PMU_FW_ACCESS_STORE = 3,
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SBI_PMU_FW_ILLEGAL_INSN = 4,
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SBI_PMU_FW_SET_TIMER = 5,
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SBI_PMU_FW_IPI_SENT = 6,
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SBI_PMU_FW_IPI_RCVD = 7,
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SBI_PMU_FW_FENCE_I_SENT = 8,
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SBI_PMU_FW_FENCE_I_RCVD = 9,
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SBI_PMU_FW_SFENCE_VMA_SENT = 10,
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SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
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SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
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SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13,
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SBI_PMU_FW_HFENCE_GVMA_SENT = 14,
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SBI_PMU_FW_HFENCE_GVMA_RCVD = 15,
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SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
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SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
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SBI_PMU_FW_HFENCE_VVMA_SENT = 18,
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SBI_PMU_FW_HFENCE_VVMA_RCVD = 19,
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SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
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SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
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SBI_PMU_FW_MAX,
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};
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/* SBI PMU event types */
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enum sbi_pmu_event_type {
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SBI_PMU_EVENT_TYPE_HW = 0x0,
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SBI_PMU_EVENT_TYPE_CACHE = 0x1,
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SBI_PMU_EVENT_TYPE_RAW = 0x2,
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SBI_PMU_EVENT_TYPE_FW = 0xf,
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};
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/* SBI PMU event types */
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enum sbi_pmu_ctr_type {
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SBI_PMU_CTR_TYPE_HW = 0x0,
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SBI_PMU_CTR_TYPE_FW,
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};
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/* Helper macros to decode event idx */
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#define SBI_PMU_EVENT_IDX_OFFSET 20
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#define SBI_PMU_EVENT_IDX_MASK 0xFFFFF
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#define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF
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#define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000
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#define SBI_PMU_EVENT_RAW_IDX 0x20000
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#define SBI_PMU_FIXED_CTR_MASK 0x07
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#define SBI_PMU_EVENT_CACHE_ID_CODE_MASK 0xFFF8
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#define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06
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#define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01
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#define SBI_PMU_EVENT_CACHE_ID_SHIFT 3
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#define SBI_PMU_EVENT_CACHE_OP_SHIFT 1
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#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
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/* Flags defined for config matching function */
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#define SBI_PMU_CFG_FLAG_SKIP_MATCH BIT(0)
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#define SBI_PMU_CFG_FLAG_CLEAR_VALUE BIT(1)
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#define SBI_PMU_CFG_FLAG_AUTO_START BIT(2)
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#define SBI_PMU_CFG_FLAG_SET_VUINH BIT(3)
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#define SBI_PMU_CFG_FLAG_SET_VSINH BIT(4)
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#define SBI_PMU_CFG_FLAG_SET_UINH BIT(5)
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#define SBI_PMU_CFG_FLAG_SET_SINH BIT(6)
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#define SBI_PMU_CFG_FLAG_SET_MINH BIT(7)
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/* Flags defined for counter start function */
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#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0)
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#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1)
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/* Flags defined for counter stop function */
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#define SBI_PMU_STOP_FLAG_RESET BIT(0)
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#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1)
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enum sbi_ext_dbcn_fid {
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SBI_EXT_DBCN_CONSOLE_WRITE = 0,
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SBI_EXT_DBCN_CONSOLE_READ = 1,
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SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2,
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};
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/* SBI STA (steal-time accounting) extension */
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enum sbi_ext_sta_fid {
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SBI_EXT_STA_STEAL_TIME_SET_SHMEM = 0,
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};
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struct sbi_sta_struct {
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__le32 sequence;
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__le32 flags;
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__le64 steal;
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u8 preempted;
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u8 pad[47];
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} __packed;
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#define SBI_SHMEM_DISABLE -1
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enum sbi_ext_nacl_fid {
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SBI_EXT_NACL_PROBE_FEATURE = 0x0,
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SBI_EXT_NACL_SET_SHMEM = 0x1,
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SBI_EXT_NACL_SYNC_CSR = 0x2,
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SBI_EXT_NACL_SYNC_HFENCE = 0x3,
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SBI_EXT_NACL_SYNC_SRET = 0x4,
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};
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enum sbi_ext_nacl_feature {
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SBI_NACL_FEAT_SYNC_CSR = 0x0,
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SBI_NACL_FEAT_SYNC_HFENCE = 0x1,
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SBI_NACL_FEAT_SYNC_SRET = 0x2,
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SBI_NACL_FEAT_AUTOSWAP_CSR = 0x3,
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};
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#define SBI_NACL_SHMEM_ADDR_SHIFT 12
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#define SBI_NACL_SHMEM_SCRATCH_OFFSET 0x0000
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#define SBI_NACL_SHMEM_SCRATCH_SIZE 0x1000
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#define SBI_NACL_SHMEM_SRET_OFFSET 0x0000
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#define SBI_NACL_SHMEM_SRET_SIZE 0x0200
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#define SBI_NACL_SHMEM_AUTOSWAP_OFFSET (SBI_NACL_SHMEM_SRET_OFFSET + \
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SBI_NACL_SHMEM_SRET_SIZE)
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#define SBI_NACL_SHMEM_AUTOSWAP_SIZE 0x0080
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#define SBI_NACL_SHMEM_UNUSED_OFFSET (SBI_NACL_SHMEM_AUTOSWAP_OFFSET + \
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SBI_NACL_SHMEM_AUTOSWAP_SIZE)
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#define SBI_NACL_SHMEM_UNUSED_SIZE 0x0580
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#define SBI_NACL_SHMEM_HFENCE_OFFSET (SBI_NACL_SHMEM_UNUSED_OFFSET + \
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SBI_NACL_SHMEM_UNUSED_SIZE)
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#define SBI_NACL_SHMEM_HFENCE_SIZE 0x0780
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#define SBI_NACL_SHMEM_DBITMAP_OFFSET (SBI_NACL_SHMEM_HFENCE_OFFSET + \
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SBI_NACL_SHMEM_HFENCE_SIZE)
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#define SBI_NACL_SHMEM_DBITMAP_SIZE 0x0080
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#define SBI_NACL_SHMEM_CSR_OFFSET (SBI_NACL_SHMEM_DBITMAP_OFFSET + \
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SBI_NACL_SHMEM_DBITMAP_SIZE)
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#define SBI_NACL_SHMEM_CSR_SIZE ((__riscv_xlen / 8) * 1024)
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#define SBI_NACL_SHMEM_SIZE (SBI_NACL_SHMEM_CSR_OFFSET + \
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SBI_NACL_SHMEM_CSR_SIZE)
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#define SBI_NACL_SHMEM_CSR_INDEX(__csr_num) \
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((((__csr_num) & 0xc00) >> 2) | ((__csr_num) & 0xff))
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#define SBI_NACL_SHMEM_HFENCE_ENTRY_SZ ((__riscv_xlen / 8) * 4)
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#define SBI_NACL_SHMEM_HFENCE_ENTRY_MAX \
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(SBI_NACL_SHMEM_HFENCE_SIZE / \
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SBI_NACL_SHMEM_HFENCE_ENTRY_SZ)
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#define SBI_NACL_SHMEM_HFENCE_ENTRY(__num) \
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(SBI_NACL_SHMEM_HFENCE_OFFSET + \
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(__num) * SBI_NACL_SHMEM_HFENCE_ENTRY_SZ)
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#define SBI_NACL_SHMEM_HFENCE_ENTRY_CONFIG(__num) \
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SBI_NACL_SHMEM_HFENCE_ENTRY(__num)
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#define SBI_NACL_SHMEM_HFENCE_ENTRY_PNUM(__num)\
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(SBI_NACL_SHMEM_HFENCE_ENTRY(__num) + (__riscv_xlen / 8))
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#define SBI_NACL_SHMEM_HFENCE_ENTRY_PCOUNT(__num)\
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(SBI_NACL_SHMEM_HFENCE_ENTRY(__num) + \
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((__riscv_xlen / 8) * 3))
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS 1
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT \
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(__riscv_xlen - SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS)
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_MASK \
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((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_BITS) - 1)
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_PEND \
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(SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_MASK << \
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SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT)
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_BITS 3
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_SHIFT \
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(SBI_NACL_SHMEM_HFENCE_CONFIG_PEND_SHIFT - \
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SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_BITS)
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS 4
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_SHIFT \
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(SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD1_SHIFT - \
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SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS)
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_MASK \
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((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_BITS) - 1)
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#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA 0x0
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#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_ALL 0x1
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#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID 0x2
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#define SBI_NACL_SHMEM_HFENCE_TYPE_GVMA_VMID_ALL 0x3
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#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA 0x4
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#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ALL 0x5
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#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID 0x6
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#define SBI_NACL_SHMEM_HFENCE_TYPE_VVMA_ASID_ALL 0x7
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_BITS 1
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_SHIFT \
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(SBI_NACL_SHMEM_HFENCE_CONFIG_TYPE_SHIFT - \
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SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_BITS)
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS 7
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_SHIFT \
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(SBI_NACL_SHMEM_HFENCE_CONFIG_RSVD2_SHIFT - \
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SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS)
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_MASK \
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((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_ORDER_BITS) - 1)
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#define SBI_NACL_SHMEM_HFENCE_ORDER_BASE 12
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#if __riscv_xlen == 32
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS 9
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS 7
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#else
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS 16
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS 14
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#endif
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_SHIFT \
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SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_MASK \
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((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_ASID_BITS) - 1)
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#define SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_MASK \
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((1UL << SBI_NACL_SHMEM_HFENCE_CONFIG_VMID_BITS) - 1)
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|
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#define SBI_NACL_SHMEM_AUTOSWAP_FLAG_HSTATUS BIT(0)
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#define SBI_NACL_SHMEM_AUTOSWAP_HSTATUS ((__riscv_xlen / 8) * 1)
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|
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#define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i))
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#define SBI_NACL_SHMEM_SRET_X_LAST 31
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|
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/* SBI spec version fields */
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#define SBI_SPEC_VERSION_DEFAULT 0x1
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#define SBI_SPEC_VERSION_MAJOR_SHIFT 24
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#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
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#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
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|
|
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/* SBI return error codes */
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|
#define SBI_SUCCESS 0
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|
#define SBI_ERR_FAILURE -1
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#define SBI_ERR_NOT_SUPPORTED -2
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|
#define SBI_ERR_INVALID_PARAM -3
|
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#define SBI_ERR_DENIED -4
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|
#define SBI_ERR_INVALID_ADDRESS -5
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#define SBI_ERR_ALREADY_AVAILABLE -6
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#define SBI_ERR_ALREADY_STARTED -7
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|
#define SBI_ERR_ALREADY_STOPPED -8
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|
#define SBI_ERR_NO_SHMEM -9
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|
|
|
extern unsigned long sbi_spec_version;
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|
struct sbiret {
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|
long error;
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|
long value;
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|
};
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|
|
|
void sbi_init(void);
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|
long __sbi_base_ecall(int fid);
|
|
struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
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|
unsigned long arg2, unsigned long arg3,
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|
unsigned long arg4, unsigned long arg5,
|
|
int fid, int ext);
|
|
#define sbi_ecall(e, f, a0, a1, a2, a3, a4, a5) \
|
|
__sbi_ecall(a0, a1, a2, a3, a4, a5, f, e)
|
|
|
|
#ifdef CONFIG_RISCV_SBI_V01
|
|
void sbi_console_putchar(int ch);
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|
int sbi_console_getchar(void);
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|
#else
|
|
static inline void sbi_console_putchar(int ch) { }
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|
static inline int sbi_console_getchar(void) { return -ENOENT; }
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|
#endif
|
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long sbi_get_mvendorid(void);
|
|
long sbi_get_marchid(void);
|
|
long sbi_get_mimpid(void);
|
|
void sbi_set_timer(uint64_t stime_value);
|
|
void sbi_shutdown(void);
|
|
void sbi_send_ipi(unsigned int cpu);
|
|
int sbi_remote_fence_i(const struct cpumask *cpu_mask);
|
|
|
|
int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask,
|
|
unsigned long start,
|
|
unsigned long size,
|
|
unsigned long asid);
|
|
int sbi_remote_hfence_gvma(const struct cpumask *cpu_mask,
|
|
unsigned long start,
|
|
unsigned long size);
|
|
int sbi_remote_hfence_gvma_vmid(const struct cpumask *cpu_mask,
|
|
unsigned long start,
|
|
unsigned long size,
|
|
unsigned long vmid);
|
|
int sbi_remote_hfence_vvma(const struct cpumask *cpu_mask,
|
|
unsigned long start,
|
|
unsigned long size);
|
|
int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
|
|
unsigned long start,
|
|
unsigned long size,
|
|
unsigned long asid);
|
|
long sbi_probe_extension(int ext);
|
|
|
|
/* Check if current SBI specification version is 0.1 or not */
|
|
static inline int sbi_spec_is_0_1(void)
|
|
{
|
|
return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
|
|
}
|
|
|
|
/* Get the major version of SBI */
|
|
static inline unsigned long sbi_major_version(void)
|
|
{
|
|
return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
|
|
SBI_SPEC_VERSION_MAJOR_MASK;
|
|
}
|
|
|
|
/* Get the minor version of SBI */
|
|
static inline unsigned long sbi_minor_version(void)
|
|
{
|
|
return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
|
|
}
|
|
|
|
/* Make SBI version */
|
|
static inline unsigned long sbi_mk_version(unsigned long major,
|
|
unsigned long minor)
|
|
{
|
|
return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << SBI_SPEC_VERSION_MAJOR_SHIFT)
|
|
| (minor & SBI_SPEC_VERSION_MINOR_MASK);
|
|
}
|
|
|
|
static inline int sbi_err_map_linux_errno(int err)
|
|
{
|
|
switch (err) {
|
|
case SBI_SUCCESS:
|
|
return 0;
|
|
case SBI_ERR_DENIED:
|
|
return -EPERM;
|
|
case SBI_ERR_INVALID_PARAM:
|
|
return -EINVAL;
|
|
case SBI_ERR_INVALID_ADDRESS:
|
|
return -EFAULT;
|
|
case SBI_ERR_NOT_SUPPORTED:
|
|
case SBI_ERR_FAILURE:
|
|
default:
|
|
return -ENOTSUPP;
|
|
};
|
|
}
|
|
|
|
extern bool sbi_debug_console_available;
|
|
int sbi_debug_console_write(const char *bytes, unsigned int num_bytes);
|
|
int sbi_debug_console_read(char *bytes, unsigned int num_bytes);
|
|
|
|
#else /* CONFIG_RISCV_SBI */
|
|
static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; }
|
|
static inline void sbi_init(void) {}
|
|
#endif /* CONFIG_RISCV_SBI */
|
|
|
|
unsigned long riscv_get_mvendorid(void);
|
|
unsigned long riscv_get_marchid(void);
|
|
unsigned long riscv_cached_mvendorid(unsigned int cpu_id);
|
|
unsigned long riscv_cached_marchid(unsigned int cpu_id);
|
|
unsigned long riscv_cached_mimpid(unsigned int cpu_id);
|
|
|
|
#if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI)
|
|
DECLARE_STATIC_KEY_FALSE(riscv_sbi_for_rfence);
|
|
#define riscv_use_sbi_for_rfence() \
|
|
static_branch_unlikely(&riscv_sbi_for_rfence)
|
|
void sbi_ipi_init(void);
|
|
#else
|
|
static inline bool riscv_use_sbi_for_rfence(void) { return false; }
|
|
static inline void sbi_ipi_init(void) { }
|
|
#endif
|
|
|
|
#endif /* _ASM_RISCV_SBI_H */
|