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79997eda0d
The timebase-frequency on PolarFire SoC is not set by an oscillator on the board, but rather by an internal divider, so move the property to mpfs.dtsi. This looks to be copy-pasta from the SiFive Unleashed as the comments in both places were almost identical. In the Unleashed's case this looks to actually be valid, as the clock is provided by a crystal on the PCB. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- CC: Conor Dooley <conor.dooley@microchip.com> CC: Daire McNamara <daire.mcnamara@microchip.com> CC: Rob Herring <robh+dt@kernel.org> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: Paul Walmsley <paul.walmsley@sifive.com> CC: Palmer Dabbelt <palmer@dabbelt.com> CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org
158 lines
2.3 KiB
Text
158 lines
2.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Original all-in-one devicetree:
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* Copyright (C) 2020-2022 - Aldec
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* Rewritten to use includes:
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* Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
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*/
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/dts-v1/;
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#include "mpfs.dtsi"
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#include "mpfs-tysom-m-fabric.dtsi"
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/ {
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model = "Aldec TySOM-M-MPFS250T-REV2";
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compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
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aliases {
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ethernet0 = &mac0;
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ethernet1 = &mac1;
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serial0 = &mmuart0;
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serial1 = &mmuart1;
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serial2 = &mmuart2;
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serial3 = &mmuart3;
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serial4 = &mmuart4;
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gpio0 = &gpio0;
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gpio1 = &gpio2;
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};
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chosen {
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stdout-path = "serial1:115200n8";
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};
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ddrc_cache_lo: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x30000000>;
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status = "okay";
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};
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ddrc_cache_hi: memory@1000000000 {
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device_type = "memory";
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reg = <0x10 0x00000000 0x0 0x40000000>;
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status = "okay";
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};
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leds {
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compatible = "gpio-leds";
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status = "okay";
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led0 {
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gpios = <&gpio1 23 1>;
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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hwmon: hwmon@45 {
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status = "okay";
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compatible = "ti,ina219";
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reg = <0x45>;
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shunt-resistor = <2000>;
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};
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};
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&gpio1 {
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interrupts = <27>, <28>, <29>, <30>,
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<31>, <32>, <33>, <47>,
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<35>, <36>, <37>, <38>,
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<39>, <40>, <41>, <42>,
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<43>, <44>, <45>, <46>,
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<47>, <48>, <49>, <50>;
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status = "okay";
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};
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&mac0 {
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status = "okay";
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phy-mode = "gmii";
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phy-handle = <&phy0>;
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};
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&mac1 {
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status = "okay";
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phy-mode = "gmii";
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phy-handle = <&phy1>;
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&mbox {
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status = "okay";
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};
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&mmc {
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max-frequency = <200000000>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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no-1-8-v;
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disable-wp;
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status = "okay";
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};
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&mmuart1 {
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status = "okay";
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};
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&mmuart2 {
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status = "okay";
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};
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&mmuart3 {
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status = "okay";
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};
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&mmuart4 {
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status = "okay";
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};
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&refclk {
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clock-frequency = <125000000>;
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};
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&rtc {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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};
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&spi1 {
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status = "okay";
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flash@0 {
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compatible = "micron,n25q128a11", "jedec,spi-nor";
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reg = <0x0>;
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spi-max-frequency = <10000000>;
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};
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};
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&syscontroller {
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status = "okay";
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};
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&usb {
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status = "okay";
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dr_mode = "host";
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};
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