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7ae04ba36b
ARCH_DMA_MINALIGN was defined as 16 - this is too small - it may be possible that two unrelated 16-byte allocations share a cache line. If one of these allocations is written using DMA and the other is written using cached write, the value that was written with DMA may be corrupted. This commit changes ARCH_DMA_MINALIGN to be 128 on PA20 and 32 on PA1.1 - that's the largest possible cache line size. As different parisc microarchitectures have different cache line size, we define arch_slab_minalign(), cache_line_size() and dma_get_cache_alignment() so that the kernel may tune slab cache parameters dynamically, based on the detected cache line size. Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Cc: stable@vger.kernel.org Signed-off-by: Helge Deller <deller@gmx.de>
77 lines
2.3 KiB
C
77 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* include/asm-parisc/cache.h
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*/
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#ifndef __ARCH_PARISC_CACHE_H
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#define __ARCH_PARISC_CACHE_H
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#include <asm/alternative.h>
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/*
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* PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
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* have 32-byte cachelines. The L1 length appears to be 16 bytes but this
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* is not clearly documented.
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*/
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#define L1_CACHE_BYTES 16
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#define L1_CACHE_SHIFT 4
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#ifndef __ASSEMBLY__
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#ifdef CONFIG_PA20
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#define ARCH_DMA_MINALIGN 128
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#else
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#define ARCH_DMA_MINALIGN 32
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#endif
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#define ARCH_KMALLOC_MINALIGN 16 /* ldcw requires 16-byte alignment */
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#define arch_slab_minalign() ((unsigned)dcache_stride)
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#define cache_line_size() dcache_stride
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#define dma_get_cache_alignment cache_line_size
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#define __read_mostly __section(".data..read_mostly")
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void parisc_cache_init(void); /* initializes cache-flushing */
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void disable_sr_hashing_asm(int); /* low level support for above */
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void disable_sr_hashing(void); /* turns off space register hashing */
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void free_sid(unsigned long);
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unsigned long alloc_sid(void);
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struct seq_file;
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extern void show_cache_info(struct seq_file *m);
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extern int split_tlb;
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extern int dcache_stride;
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extern int icache_stride;
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extern struct pdc_cache_info cache_info;
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extern struct pdc_btlb_info btlb_info;
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void parisc_setup_cache_timing(void);
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#define pdtlb(sr, addr) asm volatile("pdtlb 0(%%sr%0,%1)" \
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ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
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: : "i"(sr), "r" (addr) : "memory")
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#define pitlb(sr, addr) asm volatile("pitlb 0(%%sr%0,%1)" \
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ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
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ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
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: : "i"(sr), "r" (addr) : "memory")
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#define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
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ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
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ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
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: : "r" (addr) : "memory")
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#define asm_io_sync() asm volatile("sync" \
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ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
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ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory")
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#define asm_syncdma() asm volatile("syncdma" :::"memory")
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#endif /* ! __ASSEMBLY__ */
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/* Classes of processor wrt: disabling space register hashing */
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#define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */
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#define SRHASH_PCXL 1 /* pcxl */
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#define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */
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#endif
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