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10ca61c6c0
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC
EVK.
The MTU3a PWM pins are muxed with spi1 pins and counter external input
phase clock pins are muxed with scif2 pins. Disable these IPs when
PMOD_MTU3 macro is enabled.
Apart from this, the counter Z phase clock signal is muxed with the
SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
39 lines
1,003 B
Text
39 lines
1,003 B
Text
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G2L SMARC EVK board
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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/dts-v1/;
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/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
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#define PMOD1_SER0 1
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/*
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* To enable MTU3a PWM on PMOD0,
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* Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
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* enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
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*/
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#define PMOD_MTU3 0
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#if (PMOD_MTU3 && PMOD1_SER0)
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#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
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#endif
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#define MTU3_COUNTER_Z_PHASE_SIGNAL 0
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#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
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#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
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#endif
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#include "r9a07g044l2.dtsi"
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#include "rzg2l-smarc-som.dtsi"
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#include "rzg2l-smarc-pinfunction.dtsi"
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#include "rz-smarc-common.dtsi"
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#include "rzg2l-smarc.dtsi"
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/ {
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model = "Renesas SMARC EVK based on r9a07g044l2";
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compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
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};
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