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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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2c373e7515
Following change in the I3C bindings, the "master" suffix in I3C controller node name is discouraged (it is "controller" now) and not accurate (if device supports also target mode). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
468 lines
11 KiB
Text
468 lines
11 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2023, Intel Corporation
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*/
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/dts-v1/;
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#include <dt-bindings/reset/altr,rst-mgr-s10.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/intel,agilex5-clkmgr.h>
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/ {
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compatible = "intel,socfpga-agilex5";
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#address-cells = <2>;
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#size-cells = <2>;
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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service_reserved: svcbuffer@0 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x80000000 0x0 0x2000000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a55";
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reg = <0x0>;
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device_type = "cpu";
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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device_type = "cpu";
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a76";
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reg = <0x200>;
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device_type = "cpu";
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a76";
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reg = <0x300>;
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device_type = "cpu";
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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intc: interrupt-controller@1d000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x1d000000 0 0x10000>,
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<0x0 0x1d060000 0 0x100000>;
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ranges;
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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its: msi-controller@1d040000 {
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compatible = "arm,gic-v3-its";
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reg = <0x0 0x1d040000 0x0 0x20000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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/* Clock tree 5 main sources*/
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clocks {
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cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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cb_intosc_ls_clk: cb-intosc-ls-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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f2s_free_clk: f2s-free-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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osc1: osc1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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qspi_clk: qspi-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&intc>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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usbphy0: usbphy {
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#phy-cells = <0>;
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compatible = "usb-nop-xceiv";
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};
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soc: soc@0 {
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compatible = "simple-bus";
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ranges = <0 0 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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interrupt-parent = <&intc>;
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clkmgr: clock-controller@10d10000 {
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compatible = "intel,agilex5-clkmgr";
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reg = <0x10d10000 0x1000>;
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#clock-cells = <1>;
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};
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i2c0: i2c@10c02800 {
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compatible = "snps,designware-i2c";
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reg = <0x10c02800 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst I2C0_RESET>;
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clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
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status = "disabled";
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};
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i2c1: i2c@10c02900 {
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compatible = "snps,designware-i2c";
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reg = <0x10c02900 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst I2C1_RESET>;
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clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
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status = "disabled";
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};
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i2c2: i2c@10c02a00 {
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compatible = "snps,designware-i2c";
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reg = <0x10c02a00 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst I2C2_RESET>;
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clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
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status = "disabled";
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};
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i2c3: i2c@10c02b00 {
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compatible = "snps,designware-i2c";
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reg = <0x10c02b00 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst I2C3_RESET>;
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clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
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status = "disabled";
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};
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i2c4: i2c@10c02c00 {
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compatible = "snps,designware-i2c";
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reg = <0x10c02c00 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst I2C4_RESET>;
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clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
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status = "disabled";
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};
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i3c0: i3c@10da0000 {
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compatible = "snps,dw-i3c-master-1.00a";
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reg = <0x10da0000 0x1000>;
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#address-cells = <3>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
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status = "disabled";
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};
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i3c1: i3c@10da1000 {
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compatible = "snps,dw-i3c-master-1.00a";
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reg = <0x10da1000 0x1000>;
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#address-cells = <3>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
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status = "disabled";
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};
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gpio1: gpio@10c03300 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x10c03300 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rst GPIO1_RESET>;
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status = "disabled";
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <24>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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nand: nand-controller@10b80000 {
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compatible = "cdns,hp-nfc";
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reg = <0x10b80000 0x10000>,
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<0x10840000 0x10000>;
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reg-names = "reg", "sdma";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
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cdns,board-delay-ps = <4830>;
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status = "disabled";
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};
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ocram: sram@0 {
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compatible = "mmio-sram";
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reg = <0x00000000 0x80000>;
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ranges = <0 0 0x80000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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dmac0: dma-controller@10db0000 {
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compatible = "snps,axi-dma-1.01a";
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reg = <0x10db0000 0x500>;
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clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
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<&clkmgr AGILEX5_L4_MP_CLK>;
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clock-names = "core-clk", "cfgr-clk";
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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dma-channels = <4>;
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snps,dma-masters = <1>;
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snps,data-width = <2>;
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snps,block-size = <32767 32767 32767 32767>;
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snps,priority = <0 1 2 3>;
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snps,axi-max-burst-len = <8>;
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};
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dmac1: dma-controller@10dc0000 {
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compatible = "snps,axi-dma-1.01a";
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reg = <0x10dc0000 0x500>;
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clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
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<&clkmgr AGILEX5_L4_MP_CLK>;
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clock-names = "core-clk", "cfgr-clk";
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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dma-channels = <4>;
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snps,dma-masters = <1>;
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snps,data-width = <2>;
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snps,block-size = <32767 32767 32767 32767>;
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snps,priority = <0 1 2 3>;
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snps,axi-max-burst-len = <8>;
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};
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rst: rstmgr@10d11000 {
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compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
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reg = <0x10d11000 0x1000>;
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#reset-cells = <1>;
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};
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spi0: spi@10da4000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x10da4000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst SPIM0_RESET>;
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reset-names = "spi";
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reg-io-width = <4>;
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num-cs = <4>;
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clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
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dmas = <&dmac0 2>, <&dmac0 3>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi1: spi@10da5000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x10da5000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst SPIM1_RESET>;
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reset-names = "spi";
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reg-io-width = <4>;
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num-cs = <4>;
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clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
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status = "disabled";
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};
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sysmgr: sysmgr@10d12000 {
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compatible = "altr,sys-mgr-s10","altr,sys-mgr";
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reg = <0x10d12000 0x500>;
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};
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timer0: timer0@10c03000 {
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compatible = "snps,dw-apb-timer";
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reg = <0x10c03000 0x100>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
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clock-names = "timer";
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};
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timer1: timer1@10c03100 {
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compatible = "snps,dw-apb-timer";
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reg = <0x10c03100 0x100>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
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clock-names = "timer";
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};
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timer2: timer2@10d00000 {
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compatible = "snps,dw-apb-timer";
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reg = <0x10d00000 0x100>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
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clock-names = "timer";
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};
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timer3: timer3@10d00100 {
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compatible = "snps,dw-apb-timer";
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reg = <0x10d00100 0x100>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
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clock-names = "timer";
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};
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uart0: serial@10c02000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10c02000 0x100>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst UART0_RESET>;
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status = "disabled";
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clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
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};
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uart1: serial@10c02100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x10c02100 0x100>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst UART1_RESET>;
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status = "disabled";
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clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
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};
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usb0: usb@10b00000 {
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compatible = "snps,dwc2";
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reg = <0x10b00000 0x40000>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usbphy0>;
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phy-names = "usb2-phy";
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resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
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reset-names = "dwc2", "dwc2-ecc";
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clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>;
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clock-names = "otg";
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status = "disabled";
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};
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watchdog0: watchdog@10d00200 {
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compatible = "snps,dw-wdt";
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reg = <0x10d00200 0x100>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst WATCHDOG0_RESET>;
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clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
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status = "disabled";
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};
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watchdog1: watchdog@10d00300 {
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compatible = "snps,dw-wdt";
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reg = <0x10d00300 0x100>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst WATCHDOG1_RESET>;
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clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
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status = "disabled";
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};
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watchdog2: watchdog@10d00400 {
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compatible = "snps,dw-wdt";
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reg = <0x10d00400 0x100>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst WATCHDOG2_RESET>;
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clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
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status = "disabled";
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};
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watchdog3: watchdog@10d00500 {
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compatible = "snps,dw-wdt";
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reg = <0x10d00500 0x100>;
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interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst WATCHDOG3_RESET>;
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clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
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status = "disabled";
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};
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watchdog4: watchdog@10d00600 {
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compatible = "snps,dw-wdt";
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reg = <0x10d00600 0x100>;
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interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst WATCHDOG4_RESET>;
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clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
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status = "disabled";
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};
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qspi: spi@108d2000 {
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compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
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reg = <0x108d2000 0x100>,
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<0x10900000 0x100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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cdns,fifo-depth = <128>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x00000000>;
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clocks = <&qspi_clk>;
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status = "disabled";
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};
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};
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};
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