mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
9c39d5ab45
This release adds the devicetree files for an impressive number of new
SoC variants, though as expected these are all related to others we
already support:
- The microchip sam9x7 devicetree is now added, after the device driver
and platform code has already made it in. This is likely the last ARMv5
(!) platform to ever get added, updating the 20+ year old at91/sam9
platform wtih DDR3 memory and gigabit ethernet.
- On the Apple platform, there are now devicetree files for a number of
A-series SoCs in addition to the M-series ones, these are used
primarily in phones and tablets, but are closely related to the
already supported chips.
- Samsung Exynos 8895 and Exynos 990 are more phone SoCs used in older
Samsung Galaxy phones.
- Qualcomm Snapdragon 778G (SM7325) is another phone SoC, closely related
to the Snapdragon 7c+ Gen 3 (SC7280) used in low-end laptops.
- Rockchip RK3528 and RK3576 are new variants of their TV box and Tablet
chips, still using the older ARMv8.0 cores from RK3328/RK3399 but
with a newer process and other improvements from the RK35xx (otherwise
ARMv8.2) chips. RK3566T and RK3399-S are also added, these are just
lower-cost versions of their normal counterparts.
- TI J742S2 is a feature-reduced version of the J784s4
industrial/automotive SoC, with fewer CPU cores.
- Sophgo SG2002 is an embedded SoC with one RISC-V (C906) and one ARM
(Cortex-A53) core, at this point support is only added for running
on the RISC-V side on the LicheeRV Nano board.
A total of 92 new .dts files describing individual machines is added,
which must be a new record. The majority of these is for the newly added
chips above, notably all the Apple phones and tablets. The other new
machines include nine industrial/embedded boards with NXP i.MX6 or i.MX8
SoCs, eight for Rockchips RK35XX and one or two each for Rockchips RV1109,
RK3308, Allwinner A33, Tegra 234, Qualcomm qcs9100/sc8280xp/x1e80100,
TI AM625 and Starfive JH7110.
As usual there are also many newlyad added features in existing boards
as well as cleanups and minor bugfixes.
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Merge tag 'soc-dt-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"This release adds the devicetree files for an impressive number of new
SoC variants, though as expected these are all related to others we
already support:
- The microchip sam9x7 devicetree is now added, after the device
driver and platform code has already made it in. This is likely the
last ARMv5 (!) platform to ever get added, updating the 20+ year
old at91/sam9 platform with DDR3 memory and gigabit ethernet.
- On the Apple platform, there are now devicetree files for a number
of A-series SoCs in addition to the M-series ones, these are used
primarily in phones and tablets, but are closely related to the
already supported chips.
- Samsung Exynos 8895 and Exynos 990 are more phone SoCs used in
older Samsung Galaxy phones.
- Qualcomm Snapdragon 778G (SM7325) is another phone SoC, closely
related to the Snapdragon 7c+ Gen 3 (SC7280) used in low-end
laptops.
- Rockchip RK3528 and RK3576 are new variants of their TV box and
Tablet chips, still using the older ARMv8.0 cores from
RK3328/RK3399 but with a newer process and other improvements from
the RK35xx (otherwise ARMv8.2) chips. RK3566T and RK3399-S are also
added, these are just lower-cost versions of their normal
counterparts.
- TI J742S2 is a feature-reduced version of the J784s4
industrial/automotive SoC, with fewer CPU cores.
- Sophgo SG2002 is an embedded SoC with one RISC-V (C906) and one ARM
(Cortex-A53) core, at this point support is only added for running
on the RISC-V side on the LicheeRV Nano board.
A total of 92 new .dts files describing individual machines is added,
which must be a new record. The majority of these is for the newly
added chips above, notably all the Apple phones and tablets. The other
new machines include nine industrial/embedded boards with NXP i.MX6 or
i.MX8 SoCs, eight for Rockchips RK35XX and one or two each for
Rockchips RV1109, RK3308, Allwinner A33, Tegra 234, Qualcomm
qcs9100/sc8280xp/x1e80100, TI AM625 and Starfive JH7110.
As usual there are also many newly added features in existing boards
as well as cleanups and minor bugfixes"
* tag 'soc-dt-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (718 commits)
arm64: dts: apm: Remove unused and undocumented "bus_num" property
arm: dts: spear13xx: Remove unused and undocumented "pl022,slave-tx-disable" property
arm64: dts: amd: Remove unused and undocumented "amd,zlib-support" property
arm64: dts: lg131x: Update spi clock properties
arm64: dts: seattle: Update spi clock properties
arm64: dts: rockchip: use less broad pinctrl for pcie3x1 on Radxa E25
arm64: dts: rockchip: add Radxa ROCK 5C
dt-bindings: arm: rockchip: add Radxa ROCK 5C
arm64: dts: rockchip: orangepi-5-plus: Enable GPU
arm64: dts: rockchip: enable USB3 on NanoPC-T6
arm64: dts: rockchip: adapt regulator nodenames to preferred form
arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi GenBook
arm64: dts: rockchip: Enable HDMI display for rk3588 Cool Pi 4B
arm64: dts: rockchip: Enable HDMI0 for rk3588 Cool Pi CM5 EVB
arm64: dts: rockchip: Enable HDMI on NanoPi R6C/R6S
arm64: dts: rockchip: Enable GPU on NanoPi R6C/R6S
arm64: dts: rockchip: Enable HDMI on Hardkernel ODROID-M2
arm64: dts: rockchip: Remove non-removable flag from sdmmc on rk3576-sige5
arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
arm64: dts: allwinner: pinephone: Add mount matrix to accelerometer
...
860 lines
26 KiB
Text
860 lines
26 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2021 NXP
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*/
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#include <dt-bindings/clock/imx8ulp-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/imx8ulp-power.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "imx8ulp-pinfunc.h"
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &fec;
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gpio0 = &gpiod;
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gpio1 = &gpioe;
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gpio2 = &gpiof;
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mmc0 = &usdhc0;
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mmc1 = &usdhc1;
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mmc2 = &usdhc2;
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serial0 = &lpuart4;
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serial1 = &lpuart5;
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serial2 = &lpuart6;
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serial3 = &lpuart7;
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spi0 = &lpspi4;
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spi1 = &lpspi5;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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A35_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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cpu-idle-states = <&cpu_sleep>;
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};
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A35_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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cpu-idle-states = <&cpu_sleep>;
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};
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A35_L2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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idle-states {
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entry-method = "psci";
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cpu_sleep: cpu-sleep {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0>;
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local-timer-stop;
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entry-latency-us = <1000>;
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exit-latency-us = <700>;
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min-residency-us = <2700>;
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};
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};
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};
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gic: interrupt-controller@2d400000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
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<0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu {
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compatible = "arm,cortex-a35-pmu";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 7
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-affinity = <&A35_0>, <&A35_1>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&scmi_sensor 0>;
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trips {
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cpu_alert0: trip0 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
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};
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frosc: clock-frosc {
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compatible = "fixed-clock";
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clock-frequency = <192000000>;
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clock-output-names = "frosc";
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#clock-cells = <0>;
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};
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lposc: clock-lposc {
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compatible = "fixed-clock";
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clock-frequency = <1000000>;
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clock-output-names = "lposc";
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#clock-cells = <0>;
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};
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rosc: clock-rosc {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "rosc";
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#clock-cells = <0>;
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};
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sosc: clock-sosc {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "sosc";
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#clock-cells = <0>;
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};
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sram@2201f000 {
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compatible = "mmio-sram";
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reg = <0x0 0x2201f000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x2201f000 0x1000>;
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scmi_buf: scmi-sram-section@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x400>;
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};
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};
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firmware {
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scmi {
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compatible = "arm,scmi-smc";
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arm,smc-id = <0xc20000fe>;
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#address-cells = <1>;
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#size-cells = <0>;
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shmem = <&scmi_buf>;
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scmi_devpd: protocol@11 {
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reg = <0x11>;
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#power-domain-cells = <1>;
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};
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scmi_sensor: protocol@15 {
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reg = <0x15>;
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#thermal-sensor-cells = <1>;
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};
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};
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};
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cm33: remoteproc-cm33 {
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compatible = "fsl,imx8ulp-cm33";
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status = "disabled";
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};
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soc: soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x40000000>,
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<0x60000000 0x0 0x60000000 0x1000000>;
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s4muap: mailbox@27020000 {
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compatible = "fsl,imx8ulp-mu-s4";
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reg = <0x27020000 0x10000>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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};
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per_bridge3: bus@29000000 {
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compatible = "simple-bus";
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reg = <0x29000000 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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edma1: dma-controller@29010000 {
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compatible = "fsl,imx8ulp-edma";
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reg = <0x29010000 0x210000>;
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#dma-cells = <3>;
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dma-channels = <32>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>,
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<&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>;
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clock-names = "dma", "ch00","ch01", "ch02", "ch03",
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"ch04", "ch05", "ch06", "ch07",
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"ch08", "ch09", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15",
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"ch16", "ch17", "ch18", "ch19",
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"ch20", "ch21", "ch22", "ch23",
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"ch24", "ch25", "ch26", "ch27",
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"ch28", "ch29", "ch30", "ch31";
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};
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mu: mailbox@29220000 {
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compatible = "fsl,imx8ulp-mu";
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reg = <0x29220000 0x10000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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mu3: mailbox@29230000 {
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compatible = "fsl,imx8ulp-mu";
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reg = <0x29230000 0x10000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
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#mbox-cells = <2>;
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status = "disabled";
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};
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wdog3: watchdog@292a0000 {
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compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
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reg = <0x292a0000 0x10000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
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assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
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timeout-sec = <40>;
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};
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cgc1: clock-controller@292c0000 {
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compatible = "fsl,imx8ulp-cgc1";
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reg = <0x292c0000 0x10000>;
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#clock-cells = <1>;
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};
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|
|
pcc3: clock-controller@292d0000 {
|
|
compatible = "fsl,imx8ulp-pcc3";
|
|
reg = <0x292d0000 0x10000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
crypto: crypto@292e0000 {
|
|
compatible = "fsl,sec-v4.0";
|
|
reg = <0x292e0000 0x10000>;
|
|
ranges = <0 0x292e0000 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
sec_jr0: jr@1000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr1: jr@2000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x2000 0x1000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr2: jr@3000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x3000 0x1000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr3: jr@4000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x4000 0x1000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
tpm5: tpm@29340000 {
|
|
compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
|
|
reg = <0x29340000 0x1000>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
|
|
<&pcc3 IMX8ULP_CLK_TPM5>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c4: i2c@29370000 {
|
|
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x29370000 0x10000>;
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
|
|
<&pcc3 IMX8ULP_CLK_LPI2C4>;
|
|
clock-names = "per", "ipg";
|
|
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
|
|
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
|
|
assigned-clock-rates = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c5: i2c@29380000 {
|
|
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x29380000 0x10000>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
|
|
<&pcc3 IMX8ULP_CLK_LPI2C5>;
|
|
clock-names = "per", "ipg";
|
|
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
|
|
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
|
|
assigned-clock-rates = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart4: serial@29390000 {
|
|
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x29390000 0x1000>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart5: serial@293a0000 {
|
|
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x293a0000 0x1000>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi4: spi@293b0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x293b0000 0x10000>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
|
|
<&pcc3 IMX8ULP_CLK_LPSPI4>;
|
|
clock-names = "per", "ipg";
|
|
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
|
|
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
|
|
assigned-clock-rates = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpspi5: spi@293c0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
|
|
reg = <0x293c0000 0x10000>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
|
|
<&pcc3 IMX8ULP_CLK_LPSPI5>;
|
|
clock-names = "per", "ipg";
|
|
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
|
|
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
|
|
assigned-clock-rates = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
per_bridge4: bus@29800000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x29800000 0x800000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
pcc4: clock-controller@29800000 {
|
|
compatible = "fsl,imx8ulp-pcc4";
|
|
reg = <0x29800000 0x10000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
flexspi2: spi@29810000 {
|
|
compatible = "nxp,imx8ulp-fspi";
|
|
reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
|
|
reg-names = "fspi_base", "fspi_mmap";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>,
|
|
<&pcc4 IMX8ULP_CLK_FLEXSPI2>;
|
|
clock-names = "fspi_en", "fspi";
|
|
assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
|
|
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c6: i2c@29840000 {
|
|
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x29840000 0x10000>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
|
|
<&pcc4 IMX8ULP_CLK_LPI2C6>;
|
|
clock-names = "per", "ipg";
|
|
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
|
|
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
|
|
assigned-clock-rates = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpi2c7: i2c@29850000 {
|
|
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
|
|
reg = <0x29850000 0x10000>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
|
|
<&pcc4 IMX8ULP_CLK_LPI2C7>;
|
|
clock-names = "per", "ipg";
|
|
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
|
|
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
|
|
assigned-clock-rates = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart6: serial@29860000 {
|
|
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x29860000 0x1000>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
lpuart7: serial@29870000 {
|
|
compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
|
|
reg = <0x29870000 0x1000>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
|
|
clock-names = "ipg";
|
|
status = "disabled";
|
|
};
|
|
|
|
sai4: sai@29880000 {
|
|
compatible = "fsl,imx8ulp-sai";
|
|
reg = <0x29880000 0x10000>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>,
|
|
<&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
|
|
<&cgc1 IMX8ULP_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
|
dmas = <&edma1 67 0 1>, <&edma1 68 0 0>;
|
|
dma-names = "rx", "tx";
|
|
#sound-dai-cells = <0>;
|
|
fsl,dataline = <0 0x03 0x03>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai5: sai@29890000 {
|
|
compatible = "fsl,imx8ulp-sai";
|
|
reg = <0x29890000 0x10000>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>,
|
|
<&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
|
|
<&cgc1 IMX8ULP_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
|
dmas = <&edma1 69 0 1>, <&edma1 70 0 0>;
|
|
dma-names = "rx", "tx";
|
|
#sound-dai-cells = <0>;
|
|
fsl,dataline = <0 0x0f 0x0f>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iomuxc1: pinctrl@298c0000 {
|
|
compatible = "fsl,imx8ulp-iomuxc1";
|
|
reg = <0x298c0000 0x10000>;
|
|
};
|
|
|
|
usdhc0: mmc@298d0000 {
|
|
compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
|
|
reg = <0x298d0000 0x10000>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
|
|
<&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
|
|
<&pcc4 IMX8ULP_CLK_USDHC0>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
|
|
assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>,
|
|
<&pcc4 IMX8ULP_CLK_USDHC0>;
|
|
assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>;
|
|
assigned-clock-rates = <389283840>, <389283840>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc1: mmc@298e0000 {
|
|
compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
|
|
reg = <0x298e0000 0x10000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
|
|
<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
|
|
<&pcc4 IMX8ULP_CLK_USDHC1>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
|
|
assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
|
|
<&pcc4 IMX8ULP_CLK_USDHC1>;
|
|
assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
|
|
assigned-clock-rates = <194641920>, <194641920>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: mmc@298f0000 {
|
|
compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
|
|
reg = <0x298f0000 0x10000>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
|
|
<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
|
|
<&pcc4 IMX8ULP_CLK_USDHC2>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
|
|
assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
|
|
<&pcc4 IMX8ULP_CLK_USDHC2>;
|
|
assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
|
|
assigned-clock-rates = <194641920>, <194641920>;
|
|
fsl,tuning-start-tap = <20>;
|
|
fsl,tuning-step = <2>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg1: usb@29900000 {
|
|
compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
|
|
reg = <0x29900000 0x200>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_USB0>;
|
|
power-domains = <&scmi_devpd IMX8ULP_PD_USB0>;
|
|
phys = <&usbphy1>;
|
|
fsl,usbmisc = <&usbmisc1 0>;
|
|
ahb-burst-config = <0x0>;
|
|
tx-burst-size-dword = <0x8>;
|
|
rx-burst-size-dword = <0x8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc1: usbmisc@29900200 {
|
|
compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
|
|
"fsl,imx6q-usbmisc";
|
|
reg = <0x29900200 0x200>;
|
|
#index-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy1: usb-phy@29910000 {
|
|
compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
|
|
reg = <0x29910000 0x10000>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg2: usb@29920000 {
|
|
compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
|
|
reg = <0x29920000 0x200>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_USB1>;
|
|
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
|
|
phys = <&usbphy2>;
|
|
fsl,usbmisc = <&usbmisc2 0>;
|
|
ahb-burst-config = <0x0>;
|
|
tx-burst-size-dword = <0x8>;
|
|
rx-burst-size-dword = <0x8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc2: usbmisc@29920200 {
|
|
compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
|
|
"fsl,imx6q-usbmisc";
|
|
reg = <0x29920200 0x200>;
|
|
#index-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy2: usb-phy@29930000 {
|
|
compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
|
|
reg = <0x29930000 0x10000>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
fec: ethernet@29950000 {
|
|
compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
|
|
reg = <0x29950000 0x10000>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int0";
|
|
fsl,num-tx-queues = <1>;
|
|
fsl,num-rx-queues = <1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gpioe: gpio@2d000000 {
|
|
compatible = "fsl,imx8ulp-gpio";
|
|
reg = <0x2d000000 0x1000>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
|
|
<&pcc4 IMX8ULP_CLK_PCTLE>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc1 0 32 24>;
|
|
};
|
|
|
|
gpiof: gpio@2d010000 {
|
|
compatible = "fsl,imx8ulp-gpio";
|
|
reg = <0x2d010000 0x1000>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
|
|
<&pcc4 IMX8ULP_CLK_PCTLF>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc1 0 64 32>;
|
|
};
|
|
|
|
per_bridge5: bus@2d800000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x2d800000 0x800000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
edma2: dma-controller@2d800000 {
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compatible = "fsl,imx8ulp-edma";
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reg = <0x2d800000 0x210000>;
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#dma-cells = <3>;
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dma-channels = <32>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>,
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<&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>,
|
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<&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>,
|
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<&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>,
|
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<&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>,
|
|
<&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>,
|
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<&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>,
|
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<&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>,
|
|
<&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>,
|
|
<&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>,
|
|
<&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>,
|
|
<&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>,
|
|
<&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>,
|
|
<&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>,
|
|
<&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>,
|
|
<&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>,
|
|
<&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>;
|
|
clock-names = "dma", "ch00","ch01", "ch02", "ch03",
|
|
"ch04", "ch05", "ch06", "ch07",
|
|
"ch08", "ch09", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24", "ch25", "ch26", "ch27",
|
|
"ch28", "ch29", "ch30", "ch31";
|
|
};
|
|
|
|
cgc2: clock-controller@2da60000 {
|
|
compatible = "fsl,imx8ulp-cgc2";
|
|
reg = <0x2da60000 0x10000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pcc5: clock-controller@2da70000 {
|
|
compatible = "fsl,imx8ulp-pcc5";
|
|
reg = <0x2da70000 0x10000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
sai6: sai@2da90000 {
|
|
compatible = "fsl,imx8ulp-sai";
|
|
reg = <0x2da90000 0x10000>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>,
|
|
<&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
|
|
<&cgc1 IMX8ULP_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
|
dmas = <&edma2 71 0 1>, <&edma2 72 0 0>;
|
|
dma-names = "rx", "tx";
|
|
#sound-dai-cells = <0>;
|
|
fsl,dataline = <0 0x0f 0x0f>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sai7: sai@2daa0000 {
|
|
compatible = "fsl,imx8ulp-sai";
|
|
reg = <0x2daa0000 0x10000>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>,
|
|
<&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
|
|
<&cgc1 IMX8ULP_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
|
dmas = <&edma2 73 0 1>, <&edma2 74 0 0>;
|
|
dma-names = "rx", "tx";
|
|
#sound-dai-cells = <0>;
|
|
fsl,dataline = <0 0x0f 0x0f>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif: spdif@2dab0000 {
|
|
compatible = "fsl,imx8ulp-spdif";
|
|
reg = <0x2dab0000 0x10000>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */
|
|
<&sosc>, /* 0, extal */
|
|
<&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */
|
|
<&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */
|
|
<&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */
|
|
<&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */
|
|
<&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */
|
|
<&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */
|
|
<&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */
|
|
<&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */
|
|
clock-names = "core", "rxtx0",
|
|
"rxtx1", "rxtx2",
|
|
"rxtx3", "rxtx4",
|
|
"rxtx5", "rxtx6",
|
|
"rxtx7", "spba";
|
|
dmas = <&edma2 75 0 5>, <&edma2 76 0 4>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gpiod: gpio@2e200000 {
|
|
compatible = "fsl,imx8ulp-gpio";
|
|
reg = <0x2e200000 0x1000>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
|
|
<&pcc5 IMX8ULP_CLK_RGPIOD>;
|
|
clock-names = "gpio", "port";
|
|
gpio-ranges = <&iomuxc1 0 0 24>;
|
|
};
|
|
};
|
|
};
|