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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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7de8294925
The bootloader adds MTD partitions in this subnode if present, or in the spi-nor node itself otherwise. Setting #size-cells in MTD nodes itself is deprecated by mtd.yaml. Fix all this by adding an empty partitions node which the bootloader will fill with configured MTD partitions. Remove the deprecated properties as well. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
333 lines
8.6 KiB
Text
333 lines
8.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright 2020-2021 TQ-Systems GmbH
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*/
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#include "imx8mn.dtsi"
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/ {
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model = "TQ-Systems i.MX8MN TQMa8MxNL";
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compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
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memory@40000000 {
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device_type = "memory";
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/* our minimum RAM config will be 1024 MiB */
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reg = <0x00000000 0x40000000 0 0x40000000>;
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};
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/* e-MMC IO, needed for HS modes */
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reg_vcc1v8: regulator-vcc1v8 {
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compatible = "regulator-fixed";
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regulator-name = "TQMA8MXNL_VCC1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reg_vcc3v3: regulator-vcc3v3 {
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compatible = "regulator-fixed";
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regulator-name = "TQMA8MXNL_VCC3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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/* 640 MiB */
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size = <0 0x28000000>;
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/* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
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alloc-ranges = <0 0x40000000 0 0x78000000>;
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linux,cma-default;
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};
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};
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};
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&A53_0 {
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cpu-supply = <&buck2_reg>;
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};
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&flexspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi>;
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status = "okay";
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flash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <84000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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sensor0: temperature-sensor@1b {
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compatible = "nxp,se97b", "jedec,jc-42.4-temp";
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reg = <0x1b>;
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};
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pca9450: pmic@25 {
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compatible = "nxp,pca9450a";
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reg = <0x25>;
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/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
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pinctrl-0 = <&pinctrl_pmic>;
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pinctrl-names = "default";
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interrupt-parent = <&gpio1>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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regulators {
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/* V_0V85_SOC: 0.85 .. 0.95 */
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buck1_reg: BUCK1 {
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regulator-name = "BUCK1";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <950000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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/* VDD_ARM */
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buck2_reg: BUCK2 {
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regulator-name = "BUCK2";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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nxp,dvs-run-voltage = <950000>;
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nxp,dvs-standby-voltage = <850000>;
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regulator-ramp-delay = <3125>;
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};
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/* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */
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buck3_reg: BUCK3 {
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regulator-name = "BUCK3";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <950000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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/* VCC3V3 -> VMMC, ... must not be changed */
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buck4_reg: BUCK4 {
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regulator-name = "BUCK4";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
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buck5_reg: BUCK5 {
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regulator-name = "BUCK5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* V_1V1 -> RAM, ... must not be changed */
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buck6_reg: BUCK6 {
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regulator-name = "BUCK6";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* V_1V8_SNVS */
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ldo1_reg: LDO1 {
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regulator-name = "LDO1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* V_0V8_SNVS */
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ldo2_reg: LDO2 {
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regulator-name = "LDO2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* V_1V8_ANA */
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ldo3_reg: LDO3 {
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regulator-name = "LDO3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* V_0V9_MIPI */
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ldo4_reg: LDO4 {
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regulator-name = "LDO4";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* VCC SD IO - switched using SD2 VSELECT */
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ldo5_reg: LDO5 {
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regulator-name = "LDO5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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pcf85063: rtc@51 {
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compatible = "nxp,pcf85063a";
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reg = <0x51>;
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quartz-load-femtofarads = <7000>;
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};
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eeprom1: eeprom@53 {
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compatible = "nxp,se97b", "atmel,24c02";
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read-only;
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reg = <0x53>;
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pagesize = <16>;
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vcc-supply = <®_vcc3v3>;
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};
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eeprom0: eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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pagesize = <32>;
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vcc-supply = <®_vcc3v3>;
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};
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};
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&mipi_dsi {
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vddcore-supply = <&ldo4_reg>;
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vddio-supply = <&ldo3_reg>;
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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no-sd;
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no-sdio;
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vmmc-supply = <®_vcc3v3>;
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vqmmc-supply = <®_vcc1v8>;
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status = "okay";
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};
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/*
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* Attention:
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* wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
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* without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.
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*/
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_flexspi: flexspigrp {
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fsl,pins = <MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x84>,
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<MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84>,
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<MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84>,
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<MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84>,
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<MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84>,
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<MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c4>,
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<MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c4>;
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};
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pinctrl_i2c1_gpio: i2c1gpiogrp {
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fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c4>,
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<MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c4>;
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};
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pinctrl_pmic: pmicgrp {
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fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
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<MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
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<MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
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<MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
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<MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
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<MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
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<MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
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<MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
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<MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
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<MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
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<MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
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<MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
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};
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pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
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fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>,
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<MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
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<MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
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<MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
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<MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
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<MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
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<MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
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<MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
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<MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
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<MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
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<MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
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<MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
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};
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pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
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fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>,
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<MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
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<MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
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<MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
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<MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
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<MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
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<MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
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<MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
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<MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
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<MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
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<MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
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<MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>;
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};
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};
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