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4c33cb3128
DTB Overlays (.dtbo) can now be built from source files with the extension (.dtso). This makes it clear what is the content of the files and differentiates them from base DTB source files. Convert the DTB overlay source files in the arm64/freescale directory. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
69 lines
1.2 KiB
Text
69 lines
1.2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree fragment for LS1028A QDS board, serdes 7777
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*
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* Copyright 2019-2021 NXP
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*
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* Requires a LS1028A QDS board without lane B rework.
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* Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
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* disabled, plugged in slot 1.
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*/
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/dts-v1/;
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/plugin/;
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&mdio_slot1 {
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#address-cells = <1>;
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#size-cells = <0>;
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/* 4 ports on AQR412 */
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slot1_sxgmii0: ethernet-phy@0 {
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reg = <0x0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot1_sxgmii1: ethernet-phy@1 {
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reg = <0x1>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot1_sxgmii2: ethernet-phy@2 {
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reg = <0x2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot1_sxgmii3: ethernet-phy@3 {
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reg = <0x3>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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};
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&mscc_felix_ports {
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port@0 {
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status = "okay";
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phy-handle = <&slot1_sxgmii0>;
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phy-mode = "2500base-x";
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};
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port@1 {
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status = "okay";
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phy-handle = <&slot1_sxgmii1>;
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phy-mode = "2500base-x";
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};
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port@2 {
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status = "okay";
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phy-handle = <&slot1_sxgmii2>;
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phy-mode = "2500base-x";
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};
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port@3 {
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status = "okay";
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phy-handle = <&slot1_sxgmii3>;
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phy-mode = "2500base-x";
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};
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};
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&mscc_felix {
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status = "okay";
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};
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