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a702d4f016
Add support for the Libretech cottonwood board family. These 2 boards are based on the same PCB, with an RPi B form factor. The "Alta" board uses an a311d while the "Solitude" variant uses an s905d3. Co-developed-by: Da Xue <da.xue@libretech.co> Signed-off-by: Da Xue <da.xue@libretech.co> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231006103500.2015183-3-jbrunet@baylibre.com [narmstrong: squashed blue/green led inversion fix] Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
89 lines
2.4 KiB
Text
89 lines
2.4 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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/dts-v1/;
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#include <dt-bindings/clock/g12a-clkc.h>
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#include "meson-sm1.dtsi"
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#include "meson-libretech-cottonwood.dtsi"
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/ {
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compatible = "libretech,aml-s905d3-cc", "amlogic,sm1";
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model = "Libre Computer AML-S905D3-CC Solitude";
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sound {
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model = "LC-SOLITUDE";
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audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
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"TDMOUT_A IN 1", "FRDDR_B OUT 0",
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"TDMOUT_A IN 2", "FRDDR_C OUT 0",
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"TDM_A Playback", "TDMOUT_A OUT",
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"TDMOUT_B IN 0", "FRDDR_A OUT 1",
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"TDMOUT_B IN 1", "FRDDR_B OUT 1",
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"TDMOUT_B IN 2", "FRDDR_C OUT 1",
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"TDM_B Playback", "TDMOUT_B OUT",
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"TDMOUT_C IN 0", "FRDDR_A OUT 2",
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"TDMOUT_C IN 1", "FRDDR_B OUT 2",
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"TDMOUT_C IN 2", "FRDDR_C OUT 2",
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"TDM_C Playback", "TDMOUT_C OUT",
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"TDMIN_A IN 0", "TDM_A Capture",
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"TDMIN_B IN 0", "TDM_A Capture",
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"TDMIN_C IN 0", "TDM_A Capture",
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"TDMIN_A IN 13", "TDM_A Loopback",
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"TDMIN_B IN 13", "TDM_A Loopback",
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"TDMIN_C IN 13", "TDM_A Loopback",
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"TDMIN_A IN 1", "TDM_B Capture",
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"TDMIN_B IN 1", "TDM_B Capture",
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"TDMIN_C IN 1", "TDM_B Capture",
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"TDMIN_A IN 14", "TDM_B Loopback",
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"TDMIN_B IN 14", "TDM_B Loopback",
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"TDMIN_C IN 14", "TDM_B Loopback",
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"TDMIN_A IN 2", "TDM_C Capture",
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"TDMIN_B IN 2", "TDM_C Capture",
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"TDMIN_C IN 2", "TDM_C Capture",
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"TDMIN_A IN 15", "TDM_C Loopback",
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"TDMIN_B IN 15", "TDM_C Loopback",
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"TDMIN_C IN 15", "TDM_C Loopback",
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"TODDR_A IN 0", "TDMIN_A OUT",
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"TODDR_B IN 0", "TDMIN_A OUT",
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"TODDR_C IN 0", "TDMIN_A OUT",
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"TODDR_A IN 1", "TDMIN_B OUT",
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"TODDR_B IN 1", "TDMIN_B OUT",
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"TODDR_C IN 1", "TDMIN_B OUT",
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"TODDR_A IN 2", "TDMIN_C OUT",
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"TODDR_B IN 2", "TDMIN_C OUT",
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"TODDR_C IN 2", "TDMIN_C OUT",
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"Lineout", "ACODEC LOLP",
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"Lineout", "ACODEC LORP";
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};
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};
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&cpu0 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU_CLK>;
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clock-latency = <50000>;
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};
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&cpu1 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU1_CLK>;
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clock-latency = <50000>;
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};
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&cpu2 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU2_CLK>;
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clock-latency = <50000>;
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};
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&cpu3 {
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cpu-supply = <&vddcpu_b>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPU3_CLK>;
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clock-latency = <50000>;
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};
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