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d08c561325
Add power domain controller node for Amlogic A5 SoC. Signed-off-by: Hongyu Chen <hongyu.chen1@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240627-a5_secpower-v1-3-1f47dde1270c@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
50 lines
941 B
Text
50 lines
941 B
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
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*/
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#include "amlogic-a4-common.dtsi"
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#include <dt-bindings/power/amlogic,a5-pwrc.h>
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/ {
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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};
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};
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sm: secure-monitor {
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compatible = "amlogic,meson-gxbb-sm";
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pwrc: power-controller {
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compatible = "amlogic,a5-pwrc";
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#power-domain-cells = <1>;
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};
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};
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};
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