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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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724ba67515
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
615 lines
15 KiB
Text
615 lines
15 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
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*
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* Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
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*
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* Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mfd/atmel-flexcom.h>
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/microchip,lan966x.h>
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/ {
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model = "Microchip LAN966 family SoC";
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compatible = "microchip,lan966";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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clock-frequency = <600000000>;
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reg = <0x0>;
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};
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};
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clocks {
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sys_clk: sys_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <165625000>;
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};
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cpu_clk: cpu_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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};
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ddr_clk: ddr_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <300000000>;
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};
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nic_clk: nic_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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};
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clks: clock-controller@e00c00a8 {
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compatible = "microchip,lan966x-gck";
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#clock-cells = <1>;
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clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
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clock-names = "cpu", "ddr", "sys";
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reg = <0xe00c00a8 0x38>, <0xe00c02cc 0x4>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <37500000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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udc: usb@200000 {
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compatible = "microchip,lan9662-udc",
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"atmel,sama5d3-udc";
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reg = <0x00200000 0x80000>,
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<0xe0808000 0x400>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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};
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switch: switch@e0000000 {
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compatible = "microchip,lan966x-switch";
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reg = <0xe0000000 0x0100000>,
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<0xe2000000 0x0800000>;
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reg-names = "cpu", "gcb";
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "xtr", "fdma", "ana", "ptp",
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"ptp-ext";
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resets = <&reset 0>;
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reset-names = "switch";
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status = "disabled";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port0: port@0 {
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reg = <0>;
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status = "disabled";
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};
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port1: port@1 {
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reg = <1>;
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status = "disabled";
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};
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port2: port@2 {
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reg = <2>;
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status = "disabled";
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};
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port3: port@3 {
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reg = <3>;
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status = "disabled";
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};
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port4: port@4 {
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reg = <4>;
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status = "disabled";
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};
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port5: port@5 {
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reg = <5>;
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status = "disabled";
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};
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port6: port@6 {
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reg = <6>;
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status = "disabled";
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};
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port7: port@7 {
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reg = <7>;
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status = "disabled";
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};
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};
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};
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otp: otp@e0021000 {
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compatible = "microchip,lan9668-otpc", "microchip,lan9662-otpc";
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reg = <0xe0021000 0x300>;
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};
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flx0: flexcom@e0040000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0040000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0040000 0x800>;
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status = "disabled";
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usart0: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
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<&dma0 AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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clock-names = "usart";
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atmel,fifo-size = <32>;
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status = "disabled";
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};
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spi0: spi@400 {
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compatible = "atmel,at91rm9200-spi";
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reg = <0x400 0x200>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
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<&dma0 AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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clock-names = "spi_clk";
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atmel,fifo-size = <32>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c0: i2c@600 {
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compatible = "microchip,sam9x60-i2c";
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reg = <0x600 0x200>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
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<&dma0 AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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flx1: flexcom@e0044000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0044000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0044000 0x800>;
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status = "disabled";
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usart1: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
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<&dma0 AT91_XDMAC_DT_PERID(4)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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clock-names = "usart";
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atmel,fifo-size = <32>;
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status = "disabled";
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};
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spi1: spi@400 {
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compatible = "atmel,at91rm9200-spi";
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reg = <0x400 0x200>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
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<&dma0 AT91_XDMAC_DT_PERID(4)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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clock-names = "spi_clk";
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atmel,fifo-size = <32>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@600 {
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compatible = "microchip,sam9x60-i2c";
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reg = <0x600 0x200>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
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<&dma0 AT91_XDMAC_DT_PERID(4)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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trng: rng@e0048000 {
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compatible = "atmel,at91sam9g45-trng";
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reg = <0xe0048000 0x100>;
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clocks = <&nic_clk>;
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};
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aes: crypto@e004c000 {
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compatible = "atmel,at91sam9g46-aes";
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reg = <0xe004c000 0x100>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
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<&dma0 AT91_XDMAC_DT_PERID(13)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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clock-names = "aes_clk";
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};
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flx2: flexcom@e0060000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0060000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM2>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0060000 0x800>;
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status = "disabled";
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usart2: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
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<&dma0 AT91_XDMAC_DT_PERID(6)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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clock-names = "usart";
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atmel,fifo-size = <32>;
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status = "disabled";
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};
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spi2: spi@400 {
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compatible = "atmel,at91rm9200-spi";
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reg = <0x400 0x200>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
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<&dma0 AT91_XDMAC_DT_PERID(6)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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clock-names = "spi_clk";
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atmel,fifo-size = <32>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@600 {
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compatible = "microchip,sam9x60-i2c";
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reg = <0x600 0x200>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
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<&dma0 AT91_XDMAC_DT_PERID(6)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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flx3: flexcom@e0064000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0064000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0064000 0x800>;
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status = "disabled";
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usart3: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
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<&dma0 AT91_XDMAC_DT_PERID(8)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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clock-names = "usart";
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atmel,fifo-size = <32>;
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status = "disabled";
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};
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spi3: spi@400 {
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compatible = "atmel,at91rm9200-spi";
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reg = <0x400 0x200>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
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<&dma0 AT91_XDMAC_DT_PERID(8)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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clock-names = "spi_clk";
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atmel,fifo-size = <32>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@600 {
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compatible = "microchip,sam9x60-i2c";
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reg = <0x600 0x200>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
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<&dma0 AT91_XDMAC_DT_PERID(8)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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dma0: dma-controller@e0068000 {
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compatible = "microchip,sama7g5-dma";
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reg = <0xe0068000 0x1000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&nic_clk>;
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clock-names = "dma_clk";
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};
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sha: crypto@e006c000 {
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compatible = "atmel,at91sam9g46-sha";
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reg = <0xe006c000 0xec>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
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dma-names = "tx";
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clocks = <&nic_clk>;
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clock-names = "sha_clk";
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};
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flx4: flexcom@e0070000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe0070000 0x100>;
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clocks = <&clks GCK_ID_FLEXCOM4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe0070000 0x800>;
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status = "disabled";
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usart4: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
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<&dma0 AT91_XDMAC_DT_PERID(10)>;
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dma-names = "tx", "rx";
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clocks = <&nic_clk>;
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clock-names = "usart";
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atmel,fifo-size = <32>;
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status = "disabled";
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};
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spi4: spi@400 {
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compatible = "atmel,at91rm9200-spi";
|
|
reg = <0x400 0x200>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(10)>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&nic_clk>;
|
|
clock-names = "spi_clk";
|
|
atmel,fifo-size = <32>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@600 {
|
|
compatible = "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(10)>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&nic_clk>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer0: timer@e008c000 {
|
|
compatible = "snps,dw-apb-timer";
|
|
reg = <0xe008c000 0x400>;
|
|
clocks = <&nic_clk>;
|
|
clock-names = "timer";
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
watchdog: watchdog@e0090000 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0xe0090000 0x1000>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&nic_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpu_ctrl: syscon@e00c0000 {
|
|
compatible = "microchip,lan966x-cpu-syscon", "syscon";
|
|
reg = <0xe00c0000 0x350>;
|
|
};
|
|
|
|
can0: can@e081c000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
|
|
reg-names = "m_can", "message_ram";
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int0", "int1";
|
|
clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
|
|
clock-names = "hclk", "cclk";
|
|
assigned-clocks = <&clks GCK_ID_MCAN0>;
|
|
assigned-clock-rates = <40000000>;
|
|
bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: can@e0820000 {
|
|
compatible = "bosch,m_can";
|
|
reg = <0xe0820000 0xfc>, <0x00100000 0x8000>;
|
|
reg-names = "m_can", "message_ram";
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "int0", "int1";
|
|
clocks = <&clks GCK_ID_MCAN1>, <&clks GCK_ID_MCAN1>;
|
|
clock-names = "hclk", "cclk";
|
|
assigned-clocks = <&clks GCK_ID_MCAN1>;
|
|
assigned-clock-rates = <40000000>;
|
|
bosch,mram-cfg = <0x4000 0 0 64 0 0 32 32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
reset: reset-controller@e200400c {
|
|
compatible = "microchip,lan966x-switch-reset";
|
|
reg = <0xe200400c 0x4>;
|
|
reg-names = "gcb";
|
|
#reset-cells = <1>;
|
|
cpu-syscon = <&cpu_ctrl>;
|
|
};
|
|
|
|
gpio: pinctrl@e2004064 {
|
|
compatible = "microchip,lan966x-pinctrl";
|
|
reg = <0xe2004064 0xb4>,
|
|
<0xe2010024 0x138>;
|
|
resets = <&reset 0>;
|
|
reset-names = "switch";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&gpio 0 0 78>;
|
|
interrupt-controller;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
mdio0: mdio@e2004118 {
|
|
compatible = "microchip,lan966x-miim";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xe2004118 0x24>;
|
|
clocks = <&sys_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mdio1: mdio@e200413c {
|
|
compatible = "microchip,lan966x-miim";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xe200413c 0x24>,
|
|
<0xe2010020 0x4>;
|
|
clocks = <&sys_clk>;
|
|
status = "disabled";
|
|
|
|
phy0: ethernet-phy@1 {
|
|
reg = <1>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
phy1: ethernet-phy@2 {
|
|
reg = <2>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
sgpio: gpio@e2004190 {
|
|
compatible = "microchip,sparx5-sgpio";
|
|
reg = <0xe2004190 0x118>;
|
|
clocks = <&sys_clk>;
|
|
resets = <&reset 0>;
|
|
reset-names = "switch";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
sgpio_in: gpio@0 {
|
|
compatible = "microchip,sparx5-sgpio-bank";
|
|
reg = <0>;
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
|
|
sgpio_out: gpio@1 {
|
|
compatible = "microchip,sparx5-sgpio-bank";
|
|
reg = <1>;
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
};
|
|
};
|
|
|
|
hwmon: hwmon@e2010180 {
|
|
compatible = "microchip,lan9668-hwmon";
|
|
reg = <0xe2010180 0xc>,
|
|
<0xe20042a8 0xc>;
|
|
reg-names = "pvt", "fan";
|
|
clocks = <&sys_clk>;
|
|
};
|
|
|
|
serdes: serdes@e202c000 {
|
|
compatible = "microchip,lan966x-serdes";
|
|
reg = <0xe202c000 0x9c>,
|
|
<0xe2004010 0x4>;
|
|
#phy-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@e8c11000 {
|
|
compatible = "arm,gic-400", "arm,cortex-a7-gic";
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-controller;
|
|
reg = <0xe8c11000 0x1000>,
|
|
<0xe8c12000 0x2000>,
|
|
<0xe8c14000 0x2000>,
|
|
<0xe8c16000 0x2000>;
|
|
};
|
|
};
|
|
};
|