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f45a4399c1
According to the vendor kernel, the Exynos8895 SoC has an SPI configuration that matches with the Exynos850 one. SPI FIFO depth is 64 bytes for all SPI blocks. All blocks have DIV_4 as the default internal clock divider, and an internal loopback mode to run a loopback test. Reuse the samsung,exynos850-spi compatible. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20241020182121.377969-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
194 lines
5 KiB
YAML
194 lines
5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/samsung,spi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung S3C/S5P/Exynos SoC SPI controller
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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description:
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All the SPI controller nodes should be represented in the aliases node using
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the following format 'spi{n}' where n is a unique number for the alias.
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properties:
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compatible:
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oneOf:
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- enum:
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- google,gs101-spi
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- samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
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- samsung,s3c6410-spi
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- samsung,s5pv210-spi # for S5PV210 and S5PC110
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- samsung,exynos4210-spi
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- samsung,exynos5433-spi
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- samsung,exynos850-spi
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- samsung,exynosautov9-spi
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- tesla,fsd-spi
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- items:
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- enum:
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- samsung,exynos8895-spi
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- const: samsung,exynos850-spi
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- const: samsung,exynos7-spi
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deprecated: true
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clocks:
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minItems: 2
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maxItems: 3
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clock-names:
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minItems: 2
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maxItems: 3
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dmas:
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minItems: 2
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maxItems: 2
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dma-names:
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items:
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- const: tx
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- const: rx
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interrupts:
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maxItems: 1
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no-cs-readback:
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description:
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The CS line is disconnected, therefore the device should not operate
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based on CS signalling.
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type: boolean
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num-cs:
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minimum: 1
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maximum: 4
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default: 1
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samsung,spi-src-clk:
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description:
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If the spi controller includes a internal clock mux to select the clock
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source for the spi bus clock, this property can be used to indicate the
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clock to be used for driving the spi bus clock. If not specified, the
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clock number 0 is used as default.
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- clock-names
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- interrupts
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- reg
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynos5433-spi
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- samsung,exynosautov9-spi
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: spi
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- enum:
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- spi_busclk0
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- spi_busclk1
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- spi_busclk2
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- spi_busclk3
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- const: spi_ioclk
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else:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: spi
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- enum:
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- spi_busclk0
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- spi_busclk1
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- spi_busclk2
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- spi_busclk3
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos5433.h>
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#include <dt-bindings/clock/samsung,s2mps11.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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spi@14d30000 {
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compatible = "samsung,exynos5433-spi";
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reg = <0x14d30000 0x100>;
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interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&pdma0 11>, <&pdma0 10>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cmu_peric CLK_PCLK_SPI1>,
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<&cmu_peric CLK_SCLK_SPI1>,
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<&cmu_peric CLK_SCLK_IOCLK_SPI1>;
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clock-names = "spi",
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"spi_busclk0",
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"spi_ioclk";
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samsung,spi-src-clk = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_bus>;
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num-cs = <1>;
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cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
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audio-codec@0 {
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compatible = "wlf,wm5110";
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reg = <0x0>;
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spi-max-frequency = <20000000>;
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interrupt-parent = <&gpa0>;
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interrupts = <4 IRQ_TYPE_NONE>;
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clocks = <&pmu_system_controller 0>,
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<&s2mps13_osc S2MPS11_CLK_BT>;
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clock-names = "mclk1", "mclk2";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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wlf,micd-detect-debounce = <300>;
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wlf,micd-bias-start-time = <0x1>;
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wlf,micd-rate = <0x7>;
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wlf,micd-dbtime = <0x2>;
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wlf,micd-force-micbias;
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wlf,micd-configs = <0x0 1 0>;
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wlf,hpdet-channel = <1>;
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wlf,gpsw = <0x1>;
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wlf,inmode = <2 0 2 0>;
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wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
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wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
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/* core supplies */
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AVDD-supply = <&ldo18_reg>;
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DBVDD1-supply = <&ldo18_reg>;
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CPVDD-supply = <&ldo18_reg>;
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DBVDD2-supply = <&ldo18_reg>;
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DBVDD3-supply = <&ldo18_reg>;
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SPKVDDL-supply = <&ldo18_reg>;
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SPKVDDR-supply = <&ldo18_reg>;
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controller-data {
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samsung,spi-feedback-delay = <0>;
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};
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};
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};
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