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fa0321ba51
Document the Broadcom STB memory controller which is a trivial binding for now with a set of compatible strings and single register. Since we introduce this binding, the section in Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt is removed and this binding is referenced instead. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> [krzk: correct path in brcm,brcmstb.txt] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220812222533.2428033-2-f.fainelli@gmail.com
52 lines
1.4 KiB
YAML
52 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Memory controller (MEMC) for Broadcom STB
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maintainers:
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- Florian Fainelli <f.fainelli@gmail.com>
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properties:
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compatible:
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items:
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- enum:
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- brcm,brcmstb-memc-ddr-rev-b.1.x
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- brcm,brcmstb-memc-ddr-rev-b.2.0
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- brcm,brcmstb-memc-ddr-rev-b.2.1
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- brcm,brcmstb-memc-ddr-rev-b.2.2
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- brcm,brcmstb-memc-ddr-rev-b.2.3
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- brcm,brcmstb-memc-ddr-rev-b.2.5
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- brcm,brcmstb-memc-ddr-rev-b.2.6
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- brcm,brcmstb-memc-ddr-rev-b.2.7
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- brcm,brcmstb-memc-ddr-rev-b.2.8
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- brcm,brcmstb-memc-ddr-rev-b.3.0
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- brcm,brcmstb-memc-ddr-rev-b.3.1
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- brcm,brcmstb-memc-ddr-rev-c.1.0
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- brcm,brcmstb-memc-ddr-rev-c.1.1
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- brcm,brcmstb-memc-ddr-rev-c.1.2
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- brcm,brcmstb-memc-ddr-rev-c.1.3
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- brcm,brcmstb-memc-ddr-rev-c.1.4
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- const: brcm,brcmstb-memc-ddr
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reg:
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maxItems: 1
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clock-frequency:
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description: DDR PHY frequency in Hz
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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memory-controller@9902000 {
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compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1", "brcm,brcmstb-memc-ddr";
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reg = <0x9902000 0x600>;
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clock-frequency = <2133000000>;
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};
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