linux/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
Fei Shao 8fe3ee95da dt-bindings: display: mediatek: dp: Reference common DAI properties
The MediaTek DP hardware supports audio and exposes a DAI, so the
'#sound-dai-cells' property is needed for describing the DAI links.

Reference the dai-common.yaml schema to allow '#sound-dai-cells' to be
used, and filter out non-DP compatibles as MediaTek eDP in the same
binding doesn't support audio.

This fixes dtbs_check error:
  '#sound-dai-cells' does not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Fei Shao <fshao@chromium.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20241105090207.3892242-1-fshao@chromium.org/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2024-12-30 14:38:05 +00:00

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YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Display Port Controller
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Jitao shi <jitao.shi@mediatek.com>
description: |
MediaTek DP and eDP are different hardwares and there are some features
which are not supported for eDP. For example, audio is not supported for
eDP. Therefore, we need to use two different compatibles to describe them.
In addition, We just need to enable the power domain of DP, so the clock
of DP is generated by itself and we are not using other PLL to generate
clocks.
properties:
compatible:
enum:
- mediatek,mt8188-dp-tx
- mediatek,mt8188-edp-tx
- mediatek,mt8195-dp-tx
- mediatek,mt8195-edp-tx
reg:
maxItems: 1
nvmem-cells:
maxItems: 1
description: efuse data for display port calibration
nvmem-cell-names:
const: dp_calibration_data
power-domains:
maxItems: 1
interrupts:
maxItems: 1
'#sound-dai-cells':
const: 0
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input endpoint of the controller, usually dp_intf
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Output endpoint of the controller
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
description: |
number of lanes supported by the hardware.
The possible values:
0 - For 1 lane enabled in IP.
0 1 - For 2 lanes enabled in IP.
0 1 2 3 - For 4 lanes enabled in IP.
minItems: 1
maxItems: 4
required:
- data-lanes
required:
- port@0
- port@1
max-linkrate-mhz:
enum: [ 1620, 2700, 5400, 8100 ]
description: maximum link rate supported by the hardware.
required:
- compatible
- reg
- interrupts
- ports
- max-linkrate-mhz
allOf:
- $ref: /schemas/sound/dai-common.yaml#
- if:
not:
properties:
compatible:
contains:
enum:
- mediatek,mt8188-dp-tx
- mediatek,mt8195-dp-tx
then:
properties:
'#sound-dai-cells': false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/mt8195-power.h>
dptx@1c600000 {
compatible = "mediatek,mt8195-dp-tx";
reg = <0x1c600000 0x8000>;
power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
max-linkrate-mhz = <8100>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dptx_in: endpoint {
remote-endpoint = <&dp_intf0_out>;
};
};
port@1 {
reg = <1>;
dptx_out: endpoint {
data-lanes = <0 1 2 3>;
};
};
};
};