Changes are all over the place, but very little sticks out as
noteworthy.
There is a new misc driver for the Raspberry Pi 5's RP1 multifunction
I/O chip, along with hooking it up to the pinctrl and clk frameworks.
The reset controller and memory subsystems have mainly small updates,
but there are two new reset drivers for the K230 and VC1800B SoCs,
and new memory driver support for Tegra264.
The ARM SMCCC and SCMI firmware drivers gain a few more features that
should help them be supported across more environments. Similarly,
the SoC specific firmware on Tegra and Qualcomm get minor enhancements
and chip support.
In the drivers/soc/ directory, the ASPEED LPC snoop driver gets an
overhaul for code robustness, the Tegra and Qualcomm and NXP drivers
grow to support more chips, while the Hisilicon, Mediatek and Renesas
drivers see mostly janitorial fixes.
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Merge tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"Changes are all over the place, but very little sticks out as
noteworthy.
There is a new misc driver for the Raspberry Pi 5's RP1 multifunction
I/O chip, along with hooking it up to the pinctrl and clk frameworks.
The reset controller and memory subsystems have mainly small updates,
but there are two new reset drivers for the K230 and VC1800B SoCs, and
new memory driver support for Tegra264.
The ARM SMCCC and SCMI firmware drivers gain a few more features that
should help them be supported across more environments. Similarly, the
SoC specific firmware on Tegra and Qualcomm get minor enhancements and
chip support.
In the drivers/soc/ directory, the ASPEED LPC snoop driver gets an
overhaul for code robustness, the Tegra and Qualcomm and NXP drivers
grow to support more chips, while the Hisilicon, Mediatek and Renesas
drivers see mostly janitorial fixes"
* tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (100 commits)
bus: del unnecessary init var
soc: fsl: qe: convert set_multiple() to returning an integer
pinctrl: rp1: use new GPIO line value setter callbacks
soc: hisilicon: kunpeng_hccs: Fix incorrect log information
dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible
dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel
dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface
soc: qcom: socinfo: Add support to retrieve APPSBL build details
soc: qcom: pmic_glink: fix OF node leak
soc: qcom: spmi-pmic: add more PMIC SUBTYPE IDs
soc: qcom: socinfo: Add PM7550 & PMIV0108 PMICs
soc: qcom: socinfo: Add SoC IDs for SM7635 family
dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family
firmware: qcom: scm: request the waitqueue irq *after* initializing SCM
firmware: qcom: scm: initialize tzmem before marking SCM as available
firmware: qcom: scm: take struct device as argument in SHM bridge enable
firmware: qcom: scm: remove unused arguments from SHM bridge routines
soc: qcom: rpmh-rsc: Add RSC version 4 support
memory: tegra: Add Tegra264 MC and EMC support
firmware: tegra: bpmp: Fix build failure for tegra264-only config
...
This branch includes a change shared with the clk tree for adding
the missing PPU0 reset on the A523.
The PM domain DT binding immutable branch is also included, which
brings in v6.16-rc2, as well as PM domain bindings for other platforms.
Other changes include:
- RGB666 LCD pin definitions for the V3s PE pins and V3 PD pins
- node order fixes for the A523 dtsi
- UART1 pin definitions for A523
- Allwinner board DT binding cleanup
- EMAC support on A100/A133
- Enabled on the Liontron H-A133L board
- SID efuse, power controllers and GPU added for A523
- A523 GPU enabled on all existing boards
New boards:
- Xunlong OrangePi 4A with the Allwinner T527 SoC.
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Merge tag 'sunxi-dt-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Allwinner device tree changes for 6.17
This branch includes a change shared with the clk tree for adding
the missing PPU0 reset on the A523.
The PM domain DT binding immutable branch is also included, which
brings in v6.16-rc2, as well as PM domain bindings for other platforms.
Other changes include:
- RGB666 LCD pin definitions for the V3s PE pins and V3 PD pins
- node order fixes for the A523 dtsi
- UART1 pin definitions for A523
- Allwinner board DT binding cleanup
- EMAC support on A100/A133
- Enabled on the Liontron H-A133L board
- SID efuse, power controllers and GPU added for A523
- A523 GPU enabled on all existing boards
New boards:
- Xunlong OrangePi 4A with the Allwinner T527 SoC.
* tag 'sunxi-dt-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
arm64: dts: allwinner: a523: enable Mali GPU for all boards
arm64: dts: allwinner: a523: add Mali GPU node
arm64: dts: allwinner: a523: Add power controller device nodes
dt-bindings: power: Add A523 PPU and PCK600 power controllers
arm64: dts: allwinner: A523: Add SID controller node
arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
arm64: dts: allwinner: a100: Add EMAC support
arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
dt-bindings: arm: sunxi: Combine board variants into enums
dt-bindings: power: qcom,rpmpd: document the Milos RPMh Power Domains
arm64: dts: allwinner: t527: Add OrangePi 4A board
arm64: dts: allwinner: a523: Add UART1 pins
arm64: dts: allwinner: a523: Move rgmii0 pins to correct location
arm64: dts: allwinner: a523: Move mmc nodes to correct position
dt-bindings: arm: sunxi: Add Xunlong OrangePi 4A board
ARM: dts: sun8i: v3: Add RGB666 LCD PD pins definition
ARM: dts: sun8i: v3s: Add RGB666 LCD PE pins definition
dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen
dt-bindings: rockchip: pmu: Add compatible for RK3528
...
Link: https://lore.kernel.org/r/aHaQFe3Lr8Qzyb1M@wens.tw
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The BPMP firmware on Tegra264 defines a set of IDs for clock and reset
resources. These are not enumerations but provided by hardware, and 0 is
a reserved value, hence the numbering starts at 1.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Introduces a reset controller driver for the Kendryte K230 SoC,
resposible for managing the reset functionality of the CPUs and
various sub-modules.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250613-k230-reset-v4-1-e5266d2be440@pigmoral.tech
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
There is a PPU0 reset control bit in the same register as the PPU1
reset control. This missing reset control is for the PCK-600 unit
in the SoC. Manual tests show that the reset control indeed exists,
and if not configured, the system will hang when the PCK-600 registers
are accessed.
Add a reset entry for it at the end of the existing ones.
Fixes: 52dbf84857 ("dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250619171025.3359384-2-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Updates are across the usual driver subsystems with SoC specific drivers:
- added soc specicific drivers for sophgo cv1800 and sg2044, qualcomm
sm8750, and amlogic c3 and s4 chips.
- cache controller updates for sifive chips, plus binding changes for
other cache descriptions.
- memory controller drivers for mediatek mt6893, stm32 and cleanups for a
few more drivers
- reset controller drivers for T-Head TH1502, Sophgo sg2044 and
Renesas RZ/V2H(P)
- SCMI firmware updates to better deal with buggy firmware, plus better
support for Qualcomm X1E and NXP i.MX specific interfaces
- a new platform driver for the crypto firmware on Cznic Turris Omnia/MOX
- cleanups for the TEE firmware subsystem and amdtee driver
- minor updates and fixes for freescale/nxp, qualcomm, google, aspeed,
wondermedia, ti, nxp, renesas, hisilicon, mediatek, broadcom and samsung
SoCs
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Merge tag 'soc-drivers-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"Updates are across the usual driver subsystems with SoC specific
drivers:
- added soc specicific drivers for sophgo cv1800 and sg2044, qualcomm
sm8750, and amlogic c3 and s4 chips.
- cache controller updates for sifive chips, plus binding changes for
other cache descriptions.
- memory controller drivers for mediatek mt6893, stm32 and cleanups
for a few more drivers
- reset controller drivers for T-Head TH1502, Sophgo sg2044 and
Renesas RZ/V2H(P)
- SCMI firmware updates to better deal with buggy firmware, plus
better support for Qualcomm X1E and NXP i.MX specific interfaces
- a new platform driver for the crypto firmware on Cznic Turris
Omnia/MOX
- cleanups for the TEE firmware subsystem and amdtee driver
- minor updates and fixes for freescale/nxp, qualcomm, google,
aspeed, wondermedia, ti, nxp, renesas, hisilicon, mediatek,
broadcom and samsung SoCs"
* tag 'soc-drivers-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (133 commits)
soc: aspeed: Add NULL check in aspeed_lpc_enable_snoop()
soc: aspeed: lpc: Fix impossible judgment condition
ARM: aspeed: Don't select SRAM
docs: firmware: qcom_scm: Fix kernel-doc warning
soc: fsl: qe: Consolidate chained IRQ handler install/remove
firmware: qcom: scm: Allow QSEECOM for HP EliteBook Ultra G1q
dt-bindings: mfd: qcom,tcsr: Add compatible for ipq5018
dt-bindings: cache: add QiLai compatible to ax45mp
memory: stm32_omm: Fix error handling in stm32_omm_disable_child()
dt-bindings: cache: Convert marvell,tauros2-cache to DT schema
dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema
soc: samsung: exynos-pmu: enable CPU hotplug support for gs101
MAINTAINERS: Add google,gs101-pmu-intr-gen.yaml binding file
dt-bindings: soc: samsung: exynos-pmu: gs101: add google,pmu-intr-gen phandle
dt-bindings: soc: google: Add gs101-pmu-intr-gen binding documentation
bus: fsl-mc: Use strscpy() instead of strscpy_pad()
soc: fsl: qbman: Remove const from portal->cgrs allocation type
bus: fsl_mc: Fix driver_managed_dma check
bus: fsl-mc: increase MC_CMD_COMPLETION_TIMEOUT_MS value
bus: fsl-mc: drop useless cleanup
...
Add the required LVDS reset binding for the LCD TCON.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250507201943.330111-2-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Add a YAML schema for the T-HEAD TH1520 SoC reset controller. This
controller manages resets for subsystems such as the GPU within the
TH1520 SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Link: https://lore.kernel.org/r/20250303152511.494405-2-m.wilczynski@samsung.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
vendors are all here, adding new SoC support and fixing existing code.
There are a few patches to the clk framework here as well. They've been
baking in linux-next for weeks so I'm hoping we don't have to revert
them. The disable OF node patch is probably the scariest one although it
seems unlikely that a system would be relying on a driver _not_ probing
because the clk never appeared, but you never know. Nothing looks out of
the ordinary on the driver side but that's because it's mostly a bunch
of data.
Core:
- Use dev_err_probe() in the clk registration path (Peering into the
crystal ball shows many patches that remove printks)
- Check for disabled OF nodes in of_clk_get_hw_from_clkspec()
New Drivers:
- Allwinner A523/T527 clk driver
- Qualcomm IPQ9574 NSS clk driver
- Qualcomm QCS8300 GPU and video clk drivers
- Qualcomm SDM429 RPM clks
- Qualcomm QCM6490 LPASS (low power audio) resets
- Samsung Exynos2200: driver for several clock controllers (Alive,
CMGP, HSI, PERIC/PERIS, TOP, UFS and VFS)
- Samsung Exynos7870: Driver for several clock controllers (Alive, MIF,
DISP AUD, FSYS, G3D, ISP, MFC and PERI)
- Rockchip rk3528 and rk3562 clk driver
Updates:
- Various fixes to SoC clk drivers for incorrect data, avoid touching
protected registers, etc.
- Additions for some missing clks in existing SoC clk drivers
- DT schema conversions from text to YAML
- Kconfig cleanups to allow drivers to be compiled on moar
architectures
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Here's the pile of clk driver patches. The usual suspects^Wsilicon
vendors are all here, adding new SoC support and fixing existing code.
There are a few patches to the clk framework here as well. They've
been baking in linux-next for weeks so I'm hoping we don't have to
revert them. The disable OF node patch is probably the scariest one
although it seems unlikely that a system would be relying on a driver
_not_ probing because the clk never appeared, but you never know.
Nothing looks out of the ordinary on the driver side but that's
because it's mostly a bunch of data.
Core:
- Use dev_err_probe() in the clk registration path (Peering into the
crystal ball shows many patches that remove printks)
- Check for disabled OF nodes in of_clk_get_hw_from_clkspec()
New Drivers:
- Allwinner A523/T527 clk driver
- Qualcomm IPQ9574 NSS clk driver
- Qualcomm QCS8300 GPU and video clk drivers
- Qualcomm SDM429 RPM clks
- Qualcomm QCM6490 LPASS (low power audio) resets
- Samsung Exynos2200: driver for several clock controllers (Alive,
CMGP, HSI, PERIC/PERIS, TOP, UFS and VFS)
- Samsung Exynos7870: Driver for several clock controllers (Alive,
MIF, DISP AUD, FSYS, G3D, ISP, MFC and PERI)
- Rockchip rk3528 and rk3562 clk driver
Updates:
- Various fixes to SoC clk drivers for incorrect data, avoid touching
protected registers, etc.
- Additions for some missing clks in existing SoC clk drivers
- DT schema conversions from text to YAML
- Kconfig cleanups to allow drivers to be compiled on moar
architectures"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits)
clk: qcom: Add NSS clock Controller driver for IPQ9574
clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock
dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock
clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock
dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps
clk: amlogic: a1: fix a typo
clk: amlogic: gxbb: drop non existing 32k clock parent
clk: amlogic: gxbb: drop incorrect flag on 32k clock
clk: amlogic: g12b: fix cluster A parent data
clk: amlogic: g12a: fix mmc A peripheral clock
dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles
dt-bindings: reset: fix double id on rk3562-cru reset ids
drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock
clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490
dt-bindings: clock: qcom: Add compatible for QCM6490 boards
clk: qcom: gdsc: Update the status poll timeout for GDSC
clk: qcom: gdsc: Set retain_ff before moving to HW CTRL
clk: davinci: remove support for da830
...
The i.MX8MP DSP remoteproc driver is transitioned to use the reset
framework for driving the run/stall reset bits.
Support for managing the modem remoteprocessor on the Qualocmm MSM8226,
MSM8926, and SM8750 platforms is added.
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Merge tag 'rproc-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
Pull remoteproc updates from Bjorn Andersson:
- Transition the i.MX8MP DSP remoteproc driver to use the reset
framework for driving the run/stall reset bits
- Add support for managing the modem remoteprocessor on the Qualcomm
MSM8226, MSM8926, and SM8750 platforms
* tag 'rproc-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (28 commits)
remoteproc: qcom_q6v5_pas: Make single-PD handling more robust
remoteproc: qcom_q6v5_pas: Use resource with CX PD for MSM8226
remoteproc: core: Clear table_sz when rproc_shutdown
remoteproc: sysmon: Update qcom_add_sysmon_subdev() comment
dt-bindings: remoteproc: Consolidate SC8180X and SM8150 PAS files
irqdomain: remoteproc: Switch to of_fwnode_handle()
remoteproc: qcom: pas: add minidump_id to SC7280 WPSS
remoteproc: imx_dsp_rproc: Document run_stall struct member
remoteproc: qcom: pas: Add SM8750 MPSS
dt-bindings: remoteproc: Add SM8750 MPSS
imx_dsp_rproc: Use reset controller API to control the DSP
reset: imx8mp-audiomix: Add support for DSP run/stall
reset: imx8mp-audiomix: Introduce active_low configuration option
reset: imx8mp-audiomix: Prepare the code for more reset bits
reset: imx8mp-audiomix: Add prefix for internal macro
dt-bindings: dsp: fsl,dsp: Add resets property
dt-bindings: reset: audiomix: Add reset ids for EARC and DSP
remoteproc: qcom_wcnss: Handle platforms with only single power domain
dt-bindings: remoteproc: qcom,wcnss-pil: Add support for single power-domain platforms
remoteproc: qcom_q6v5_mss: Add modem support on MSM8926
...
* clk-allwinner:
clk: sunxi-ng: add support for the A523/T527 PRCM CCU
clk: sunxi-ng: a523: add reset lines
clk: sunxi-ng: a523: add bus clock gates
clk: sunxi-ng: a523: remaining mod clocks
clk: sunxi-ng: a523: add USB mod clocks
clk: sunxi-ng: a523: add interface mod clocks
clk: sunxi-ng: a523: add system mod clocks
clk: sunxi-ng: a523: add video mod clocks
clk: sunxi-ng: a523: Add support for bus clocks
clk: sunxi-ng: Add support for the A523/T527 CCU PLLs
dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs
clk: sunxi-ng: Add support for update bit
clk: sunxi-ng: mp: provide wrappers for setting feature flags
clk: sunxi-ng: mp: introduce dual-divider clock
clk: sunxi-ng: h616: Reparent GPU clock during frequency changes
clk: sunxi-ng: h616: Add clock/reset for LCD TCON
dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset
* clk-amlogic:
clk: amlogic: a1: fix a typo
clk: amlogic: gxbb: drop non existing 32k clock parent
clk: amlogic: gxbb: drop incorrect flag on 32k clock
clk: amlogic: g12b: fix cluster A parent data
clk: amlogic: g12a: fix mmc A peripheral clock
* clk-qcom: (41 commits)
clk: qcom: Add NSS clock Controller driver for IPQ9574
clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock
dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock
clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock
dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps
drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock
clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490
dt-bindings: clock: qcom: Add compatible for QCM6490 boards
clk: qcom: gdsc: Update the status poll timeout for GDSC
clk: qcom: gdsc: Set retain_ff before moving to HW CTRL
clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable()
clk: qcom: videocc: Constify 'struct qcom_cc_desc'
clk: qcom: gpucc: Constify 'struct qcom_cc_desc'
clk: qcom: dispcc: Constify 'struct qcom_cc_desc'
clk: qcom: camcc: Constify 'struct qcom_cc_desc'
dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover
clk: qcom: Add support for Video Clock Controller on QCS8300
clk: qcom: Add support for GPU Clock Controller on QCS8300
...
Id 173 was accidentially used two times for SRST_P_DDR_HWLP and
SRST_P_DDR_PHY. This makes both resets ambiguous and also causes build
warnings like:
drivers/clk/rockchip/rst-rk3562.c:21:57: error: initialized field overwritten [-Werror=override-init]
21 | #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
| ^
drivers/clk/rockchip/rst-rk3562.c:266:9: note: in expansion of macro 'RK3562_DDRCRU_RESET_OFFSET'
266 | RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/rockchip/rst-rk3562.c:21:57: note: (near initialization for 'rk3562_register_offset[173]')
21 | #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
| ^
drivers/clk/rockchip/rst-rk3562.c:266:9: note: in expansion of macro 'RK3562_DDRCRU_RESET_OFFSET'
266 | RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
To fix that issue give SRST_P_DDR_PHY a new and now unique id.
Reported-by: Stephen Boyd <sboyd@kernel.org>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202503121743.0zcDf6nE-lkp@intel.com/
Fixes: dd113c4fef ("dt-bindings: clock: Add RK3562 cru")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250312215923.275625-1-heiko@sntech.de
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add reset ids used for EARC and DSP on i.MX8MP platform.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20250311085812.1296243-2-daniel.baluta@nxp.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
The Allwinner A523/T527 SoCs have four CCUs, this adds the binding for
the main and the PRCM R-CCU.
The source clock list differs in some annoying details, and folding this
into the existing Allwinner CCU clock binding document gets quite
unwieldy, so create a new document for these CCUs.
Add the new compatible string, along with the required input clock
lists. This conditionally describes the input clock lists, to make
adding support for the other two CCUs easier.
Also add the DT binding headers, listing all the clocks with their ID
numbers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250307002628.10684-5-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Document the device tree bindings of the rockchip rk3562 SoC
clock and reset unit.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250227105916.2340856-2-kever.yang@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs, gapless
numbers starting from zero are used.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the required clock and reset bindings for the LCD TCON.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250213172248.158447-2-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
When TF-A is used to assert/deassert the resets through SCMI, the
IDs communicated to it are different than the ones mainline Linux uses.
Import the list of SCMI reset IDs from mainline TF-A so that devicetrees
can use these IDs more easily.
Co-developed-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This reset controller is part of audio clock controller and handled by
auxiliary reset driver. Introduced defines supposed to be used together
with upcoming device tree nodes for audio clock controller fo A1 SoC.
Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241112230056.1406222-2-jan.dakinevich@salutedevices.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
some unit tests for the assigned clk rates feature in DeviceTree. On the vendor
driver side, we gained a whole pile of SoC driver support detailed below. The
majority in the diffstat is Qualcomm, but there's also quite a few Samsung and
Mediatek clk driver additions in here as well. The top vendors is quite common,
but the sheer amount of new drivers is uncommon, so I'm anticipating a larger
number of fixes for clk drivers this cycle.
Core:
- devm_clk_bulk_get_all_enabled() to return number of clks acquired
- devm_clk_hw_register_gate_parent_hw() helper to modernize drivers
- KUnit tests for clk-assigned-rates{,-u64}
New Drivers:
- Marvell PXA1908 SoC clks
- Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver
- TWL6030 clk driver
- Nuvoton Arbel BMC NPCM8XX SoC clks
- MediaTek MT6735 SoC clks
- MediaTek MT7620, MT7628 and MT7688 MMC clks
- Add a driver for gated fixed rate clocks
- Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs
- Camera, display and video clock controllers for Qualcomm SA8775P SoCs
- Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm SAR2130P
- Global, camera, display, GPU, and video clock controllers for Qualcomm
SM8475 SoCs
- RTC power domain and Battery Backup Function (VBATTB) clock support for the
Renesas RZ/G3S SoC
- Qualcomm IPQ9574 alpha PLLs
- Support for i.MX91 CCM in the i.MX93 driver
- Microchip LAN969X SoC clks
- Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and reset on
Renesas RZ/V2H(P)
- Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1
- Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP
Updates:
- Convert more clk bindings to YAML
- Various clk driver cleanups: NULL checks, add const, etc.
- Remove END/NUM #defines that count number of clks in various binding headers
- Continue moving reset drivers to drivers/reset via auxiliary bus
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The core framework gained a clk provider helper, a clk consumer
helper, and some unit tests for the assigned clk rates feature in
DeviceTree. On the vendor driver side, we gained a whole pile of SoC
driver support detailed below. The majority in the diffstat is
Qualcomm, but there's also quite a few Samsung and Mediatek clk driver
additions in here as well. The top vendors is quite common, but the
sheer amount of new drivers is uncommon, so I'm anticipating a larger
number of fixes for clk drivers this cycle.
Core:
- devm_clk_bulk_get_all_enabled() to return number of clks acquired
- devm_clk_hw_register_gate_parent_hw() helper to modernize drivers
- KUnit tests for clk-assigned-rates{,-u64}
New Drivers:
- Marvell PXA1908 SoC clks
- Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver
- TWL6030 clk driver
- Nuvoton Arbel BMC NPCM8XX SoC clks
- MediaTek MT6735 SoC clks
- MediaTek MT7620, MT7628 and MT7688 MMC clks
- Add a driver for gated fixed rate clocks
- Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs
- Camera, display and video clock controllers for Qualcomm SA8775P
SoCs
- Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm
SAR2130P
- Global, camera, display, GPU, and video clock controllers for
Qualcomm SM8475 SoCs
- RTC power domain and Battery Backup Function (VBATTB) clock support
for the Renesas RZ/G3S SoC
- Qualcomm IPQ9574 alpha PLLs
- Support for i.MX91 CCM in the i.MX93 driver
- Microchip LAN969X SoC clks
- Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and
reset on Renesas RZ/V2H(P)
- Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1
- Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP
Updates:
- Convert more clk bindings to YAML
- Various clk driver cleanups: NULL checks, add const, etc.
- Remove END/NUM #defines that count number of clks in various
binding headers
- Continue moving reset drivers to drivers/reset via auxiliary bus"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits)
clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access
clk: Fix invalid execution of clk_set_rate
clk: clk-loongson2: Fix memory corruption bug in struct loongson2_clk_provider
clk: lan966x: make it selectable for ARCH_LAN969X
clk: eyeq: add EyeQ6H west fixed factor clocks
clk: eyeq: add EyeQ6H central fixed factor clocks
clk: eyeq: add EyeQ5 fixed factor clocks
clk: eyeq: add fixed factor clocks infrastructure
clk: eyeq: require clock index with phandle in all cases
clk: fixed-factor: add clk_hw_register_fixed_factor_index() function
dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks
dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
clk: clk-axi-clkgen: make sure to enable the AXI bus clock
dt-bindings: clock: axi-clkgen: include AXI clk
clk: mmp: Add Marvell PXA1908 MPMU driver
clk: mmp: Add Marvell PXA1908 APMU driver
clk: mmp: Add Marvell PXA1908 APBCP driver
clk: mmp: Add Marvell PXA1908 APBC driver
dt-bindings: clock: Add Marvell PXA1908 clock bindings
clk: mmp: Switch to use struct u32_fract instead of custom one
...
Add device tree bindings for syscon clock and reset controllers (IMGSYS,
MFGCFG, VDECSYS and VENCSYS).
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241106111402.200940-2-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add reset, clk dt bindings headers, and update compatible
support for AST2700 clk, silicon-id in yaml.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20241023090153.1395220-2-ryan_chen@aspeedtech.com
Signed-off-by: Lee Jones <lee@kernel.org>
Add clock definitions for the main clock and reset controllers of MT6735
(apmixedsys, topckgen, infracfg and pericfg).
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241017071708.38663-2-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Block comments should align the * on each line, as checkpatch rightfully
pointed out, so fix that style issue on the newly added rk3576 headers.
Fixes: 49c04453db ("dt-bindings: clock, reset: Add support for rk3576")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20240909223149.85364-1-heiko@sntech.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add clock and reset ID defines for rk3576.
Compared to the downstream bindings written by Elaine, this uses
continous gapless IDs starting at 0. Thus all numbers are
different between downstream and upstream, but names are kept
exactly the same.
Also add documentation for the rk3576 CRU core.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/0102019199a76766-f3a2b53f-d063-458b-b0d1-dfbc2ea1893c-000000@eu-west-1.amazonses.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Introduce reset capability to EN7581 device-tree clock binding
documentation. Add reset register mapping between misc scu and pb scu
ones in order to follow the memory order. This change is not
introducing any backward compatibility issue since the EN7581 dts is not
upstream yet.
Fixes: 0a382be005 ("dt-bindings: clock: airoha: add EN7581 binding")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/28fef3e83062d5d71e7b4be4b47583f851a15bf8.1719485847.git.lorenzo@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the required clock bindings for the GPADC.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240605172049.231108-2-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
QCA8386/QCA8084 includes the clock & reset controller that is
accessed by MDIO bus. Two work modes are supported, qca8386 works
as switch mode, qca8084 works as PHY mode.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20240605124541.2711467-3-quic_luoj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
RCC driver uses '.index' to define all parent clocks instead '.names'
because the use of a name to define a parent clock is discouraged. This
is an ABI change, but the RCC driver has not yet merged, unlike all
others drivers besides Linux.
Fixes: b5be49db3d ("dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240411092453.243633-3-gabriel.fernandez@foss.st.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
These are changes that for some reason ended up not making it into the
first four branches but that should still make it into 6.9:
- A rework of the omap clock support that touches both drivers and
device tree files
- The reset controller branch changes that had a dependency on late
bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the
drivers branch
- The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree
changes that got delayed and needed some extra time in linux-next
for wider testing.
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Merge tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more ARM SoC updates from Arnd Bergmann:
"These are changes that for some reason ended up not making it into the
first four branches but that should still make it into 6.9:
- A rework of the omap clock support that touches both drivers and
device tree files
- The reset controller branch changes that had a dependency on late
bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the
drivers branch
- The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree
changes that got delayed and needed some extra time in linux-next
for wider testing"
* tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits)
soc: fsl: dpio: fix kcalloc() argument order
bus: ts-nbus: Improve error reporting
bus: ts-nbus: Convert to atomic pwm API
riscv: dts: starfive: jh7110: Add camera subsystem nodes
ARM: bcm: stop selecing CONFIG_TICK_ONESHOT
ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift
ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift
clk: ti: Improve clksel clock bit parsing for reg property
clk: ti: Handle possible address in the node name
dt-bindings: pwm: opencores: Add compatible for StarFive JH8100
dt-bindings: riscv: cpus: reg matches hart ID
reset: Instantiate reset GPIO controller for shared reset-gpios
reset: gpio: Add GPIO-based reset controller
cpufreq: do not open-code of_phandle_args_equal()
of: Add of_phandle_args_equal() helper
reset: simple: add support for Sophgo SG2042
dt-bindings: reset: sophgo: support SG2042
riscv: dts: microchip: add specific compatible for mpfs pdma
riscv: dts: microchip: add missing CAN bus clocks
ARM: brcmstb: Add debug UART entry for 74165
...
Add reset constants for using as index in driver and dts.
Value is starting again from 0 because resets are used in another device
than existing constants.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240201182409.39878-2-linux@fw-web.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
SM8650 based on the diffstat. Otherwise this is a collection of non-critical
fixes and cleanups to various clk drivers and their DT bindings. Nothing is
changed in the core clk framework this time, although there's a patch to fix a
basic clk type initialization function. In general, this pile looks to be on
the smaller side.
New Drivers:
- Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650
- Mediatek MT7988 SoC clocks
Updates:
- Update Zynqmp driver for Versal NET platforms
- Add clk driver for Versal clocking wizard IP
- Support for stm32mp25 clks
- Add glitch free PLL setting support to si5351 clk driver
- Add DSI clocks on Amlogic g12/sm1
- Add CSI and ISP clocks on Amlogic g12/sm1
- Document bindings for i.MX93 ANATOP clock driver
- Free clk_node in i.MX SCU driver for resource with different owner
- Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15
- Fix the name of the fvco in i.MX pll14xx by renaming it to fout
- Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC
- Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S
- Check reset monitor registers on Renesas RZ/G2L-alike SoCs
- Reuse reset functionality in the Renesas RZ/G2L clock driver
- Global and RPMh clock support for the Qualcomm X1E80100 SoC
- Support for the Stromer APCS PLL found in Qualcomm IPQ5018
- Add a new type of branch clock, with support for controlling separate
memory control bits, to the Qualcomm clk driver
- Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and
QRU1000
- Add a number of missing clocks related to CSI2 on Qualcomm MSM8939
- Add support for the camera clock controller on Qualcomm SC8280XP
- Correct PLL configuration in GPU and video clock controllers for
Qualcomm SM8150
- Add runtime PM support and a few missing resets to Qualcomm SM8150
video clock controller
- Fix configuration of various GCC GDSCs on Qualcomm SM8550
- Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver
- Fix up GPU and display clock controllers PLL configuration settings
on Qualcomm SM8550
- Cleanup variable init in Allwinner nkm module
- Convert various DT bindings to YAML
- A few kernel-doc fixes for Samsung SoC clock controllers
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Only a couple new SoCs have support added this time, primarily for
Qualcomm SM8650 based on the diffstat. Otherwise this is a collection
of non-critical fixes and cleanups to various clk drivers and their DT
bindings.
Nothing is changed in the core clk framework this time, although
there's a patch to fix a basic clk type initialization function. In
general, this pile looks to be on the smaller side.
New Drivers:
- Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650
- Mediatek MT7988 SoC clocks
Updates:
- Update Zynqmp driver for Versal NET platforms
- Add clk driver for Versal clocking wizard IP
- Support for stm32mp25 clks
- Add glitch free PLL setting support to si5351 clk driver
- Add DSI clocks on Amlogic g12/sm1
- Add CSI and ISP clocks on Amlogic g12/sm1
- Document bindings for i.MX93 ANATOP clock driver
- Free clk_node in i.MX SCU driver for resource with different owner
- Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15
- Fix the name of the fvco in i.MX pll14xx by renaming it to fout
- Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC
- Add interrupt controller and Ethernet clocks and resets on Renesas
RZ/G3S
- Check reset monitor registers on Renesas RZ/G2L-alike SoCs
- Reuse reset functionality in the Renesas RZ/G2L clock driver
- Global and RPMh clock support for the Qualcomm X1E80100 SoC
- Support for the Stromer APCS PLL found in Qualcomm IPQ5018
- Add a new type of branch clock, with support for controlling
separate memory control bits, to the Qualcomm clk driver
- Use above new branch type in Qualcomm ECPRI clk driver for QDU1000
and QRU1000
- Add a number of missing clocks related to CSI2 on Qualcomm MSM8939
- Add support for the camera clock controller on Qualcomm SC8280XP
- Correct PLL configuration in GPU and video clock controllers for
Qualcomm SM8150
- Add runtime PM support and a few missing resets to Qualcomm SM8150
video clock controller
- Fix configuration of various GCC GDSCs on Qualcomm SM8550
- Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver
- Fix up GPU and display clock controllers PLL configuration settings
on Qualcomm SM8550
- Cleanup variable init in Allwinner nkm module
- Convert various DT bindings to YAML
- A few kernel-doc fixes for Samsung SoC clock controllers"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits)
clk: mediatek: add drivers for MT7988 SoC
clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
dt-bindings: clock: mediatek: add clock controllers of MT7988
dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs
dt-bindings: clock: mediatek: add MT7988 clock IDs
clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes
clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes
clk: mediatek: clk-mux: Support custom parent indices for muxes
dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC
clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx
clk: starfive: Add flags argument to JH71X0__MUX macro
clk: imx: pll14xx: change naming of fvco to fout
clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks
clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu()
clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw
clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config
clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config
clk: qcom: dispcc-sm8550: Use the correct PLL configuration function
clk: qcom: dispcc-sm8550: Update disp PLL settings
clk: qcom: gpucc-sm8550: Update GPU PLL settings
...
A new drivers/cache/ subsystem is added to contain drivers for abstracting
cache flush methods on riscv and potentially others, as this is needed for
handling non-coherent DMA but several SoCs require nonstandard hardware
methods for it.
op-tee gains support for asynchronous notification with FF-A, as well
as support for a system thread for executing in secure world.
The tee, reset, bus, memory and scmi subsystems have a couple of minor
updates.
Platform specific soc driver changes include:
- Samsung Exynos gains driver support for Google GS101 (Tensor G1)
across multiple subsystems
- Qualcomm Snapdragon gains support for SM8650 and X1E along with
added features for some other SoCs
- Mediatek adds support for "Smart Voltage Scaling" on MT8186 and MT8195,
and driver support for MT8188 along with some code refactoring.
- Microchip Polarfire FPGA support for "Auto Update" of the FPGA bitstream
- Apple M1 mailbox driver is rewritten into a SoC driver
- minor updates on amlogic, mvebu, ti, zynq, imx, renesas and hisilicon
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Merge tag 'soc-drivers-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"A new drivers/cache/ subsystem is added to contain drivers for
abstracting cache flush methods on riscv and potentially others, as
this is needed for handling non-coherent DMA but several SoCs require
nonstandard hardware methods for it.
op-tee gains support for asynchronous notification with FF-A, as well
as support for a system thread for executing in secure world.
The tee, reset, bus, memory and scmi subsystems have a couple of minor
updates.
Platform specific soc driver changes include:
- Samsung Exynos gains driver support for Google GS101 (Tensor G1)
across multiple subsystems
- Qualcomm Snapdragon gains support for SM8650 and X1E along with
added features for some other SoCs
- Mediatek adds support for "Smart Voltage Scaling" on MT8186 and
MT8195, and driver support for MT8188 along with some code
refactoring.
- Microchip Polarfire FPGA support for "Auto Update" of the FPGA
bitstream
- Apple M1 mailbox driver is rewritten into a SoC driver
- minor updates on amlogic, mvebu, ti, zynq, imx, renesas and
hisilicon"
* tag 'soc-drivers-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (189 commits)
memory: ti-emif-pm: Convert to platform remove callback returning void
memory: ti-aemif: Convert to platform remove callback returning void
memory: tegra210-emc: Convert to platform remove callback returning void
memory: tegra186-emc: Convert to platform remove callback returning void
memory: stm32-fmc2-ebi: Convert to platform remove callback returning void
memory: exynos5422-dmc: Convert to platform remove callback returning void
memory: renesas-rpc-if: Convert to platform remove callback returning void
memory: omap-gpmc: Convert to platform remove callback returning void
memory: mtk-smi: Convert to platform remove callback returning void
memory: jz4780-nemc: Convert to platform remove callback returning void
memory: fsl_ifc: Convert to platform remove callback returning void
memory: fsl-corenet-cf: Convert to platform remove callback returning void
memory: emif: Convert to platform remove callback returning void
memory: brcmstb_memc: Convert to platform remove callback returning void
memory: brcmstb_dpfe: Convert to platform remove callback returning void
soc: qcom: llcc: Fix LLCC_TRP_ATTR2_CFGn offset
firmware: qcom: qseecom: fix memory leaks in error paths
dt-bindings: clock: google,gs101: rename CMU_TOP gate defines
soc: qcom: llcc: Fix typo in kernel-doc
dt-bindings: soc: qcom,aoss-qmp: document the X1E80100 Always-On Subsystem side channel
...
Add reset ID for ethwarp subsystem allowing to reset the built-in
Ethernet switch of the MediaTek MT7988 SoC.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Support is added for the new Snapdragon 8 Gen 3 mobile platform, with
support for the MTP and QRD development devices, the new Snapdragon X
Elite compute platform with QCP and CRD development/references devices,
the QCS6590/QCM6490 platform with support for the IDP development device
and the Robotics RB3gen2 board, the Huawei Honor 5X/GR5 handset
built on MSM8939, and Xiaomi Pad 6 on SM8250.
On IPQ5018 and IPQ6018 platform support for CPUfreq, USB, and one
additional QUP SPI controller is added.
CPU OPP tables are selectively enabled based on fuses, for both IPQ5332
and IPQ6018. IPQ6018 gains description of a few more SPI and UART nodes.
Common elements of the IPQ9574 RDP boards are refactored into a common
include file. IPQ9574 also gains description of its LEDs and WPS
busttons.
MSM8916 finally gets the DSP-based audio described, and this is enabled
for a variety of boards. Acer Iconia Talk S and Loncheer L8910 gains
notification LED, battery and charger support is added to Loncheer
L8150, and GPU is enabled for Samsung Galaxy Tab A.
Similariy DSP-based audio is added on MSM8939, the BAM-DMUX support is
enabled as well. The Longcheer L9100 gains RGB notification LED support,
and the wireless subsystem is enabled.
Missing SPI controllers are described on MSM8953. On MSM8996 the MPM is
enabled, to allow using wakeup interrupts. Interconnect providers, MPM
and display are added to QCM2290.
UFS, remoteprocs and WiFi is enabled for Fairphone FP5.
On Fairphone FP3 audio, WiFi and Bluetooth are enabled.
On the Robotics RB1, HDMI and the CAN bus controller are added. On
Robotics RB2 Bluetooth, the modem remoteproc and WiFi are enabled.
Bluetooth is enabled on the Robotics RB5.
On SA8775P tsens and thermal is added, as well as the random number
generator.
Sound and RTC support is added for the Acer Aspire 1.
On SC7280 DeviceTree is refactored, in order to allow non-Chrome devices
to inherit the base dtsi. Support for UFS, crypto, TrustZone based
remoteprocs, the Camera Control Interface (CCI) and random number
generator support are added. Additionally a variety of smaller fixes are
introduced.
A variety of fixes are introduced for SC8180X, in particular missing
power-domains and interconnects.
On SC8280XP the camera clock controller is added, and a number of
smaller fixes are introduced.
The display subsystem in SDM670 is described.
On SDX75 interconnect providers are added, as is USB3 and the related
PHY, which is then enabled on the IDP device.
On SM6115 interconnect providers are added and existing clients are
wired up. A UART controller is added as well.
The MPM is added, to provide wakeup interrutps, on SM6375. The modem
subsystem, and WiFi are enabled on Sony Xperia 10 IV, a few regulator
supplies are corrected.
On SM8150 the DisplayPort controller is added, for USB Type-C output,
which together with the addition of HDMI is described on the HDK board.
GPU and random number generator support are added to SM8450, and enabled
on the HDK board.
On SM8550 GPU, IPA, random number generator, missing SoundWire ports are
added, and enabled on both MTP and QRD devices.
Additionally a large number of smaller functional and DeviceTree binding
validation issues are corrected across a variety of platforms.
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Merge tag 'qcom-arm64-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm ARM64 updates for v6.8
Support is added for the new Snapdragon 8 Gen 3 mobile platform, with
support for the MTP and QRD development devices, the new Snapdragon X
Elite compute platform with QCP and CRD development/references devices,
the QCS6590/QCM6490 platform with support for the IDP development device
and the Robotics RB3gen2 board, the Huawei Honor 5X/GR5 handset
built on MSM8939, and Xiaomi Pad 6 on SM8250.
On IPQ5018 and IPQ6018 platform support for CPUfreq, USB, and one
additional QUP SPI controller is added.
CPU OPP tables are selectively enabled based on fuses, for both IPQ5332
and IPQ6018. IPQ6018 gains description of a few more SPI and UART nodes.
Common elements of the IPQ9574 RDP boards are refactored into a common
include file. IPQ9574 also gains description of its LEDs and WPS
busttons.
MSM8916 finally gets the DSP-based audio described, and this is enabled
for a variety of boards. Acer Iconia Talk S and Loncheer L8910 gains
notification LED, battery and charger support is added to Loncheer
L8150, and GPU is enabled for Samsung Galaxy Tab A.
Similariy DSP-based audio is added on MSM8939, the BAM-DMUX support is
enabled as well. The Longcheer L9100 gains RGB notification LED support,
and the wireless subsystem is enabled.
Missing SPI controllers are described on MSM8953. On MSM8996 the MPM is
enabled, to allow using wakeup interrupts. Interconnect providers, MPM
and display are added to QCM2290.
UFS, remoteprocs and WiFi is enabled for Fairphone FP5.
On Fairphone FP3 audio, WiFi and Bluetooth are enabled.
On the Robotics RB1, HDMI and the CAN bus controller are added. On
Robotics RB2 Bluetooth, the modem remoteproc and WiFi are enabled.
Bluetooth is enabled on the Robotics RB5.
On SA8775P tsens and thermal is added, as well as the random number
generator.
Sound and RTC support is added for the Acer Aspire 1.
On SC7280 DeviceTree is refactored, in order to allow non-Chrome devices
to inherit the base dtsi. Support for UFS, crypto, TrustZone based
remoteprocs, the Camera Control Interface (CCI) and random number
generator support are added. Additionally a variety of smaller fixes are
introduced.
A variety of fixes are introduced for SC8180X, in particular missing
power-domains and interconnects.
On SC8280XP the camera clock controller is added, and a number of
smaller fixes are introduced.
The display subsystem in SDM670 is described.
On SDX75 interconnect providers are added, as is USB3 and the related
PHY, which is then enabled on the IDP device.
On SM6115 interconnect providers are added and existing clients are
wired up. A UART controller is added as well.
The MPM is added, to provide wakeup interrutps, on SM6375. The modem
subsystem, and WiFi are enabled on Sony Xperia 10 IV, a few regulator
supplies are corrected.
On SM8150 the DisplayPort controller is added, for USB Type-C output,
which together with the addition of HDMI is described on the HDK board.
GPU and random number generator support are added to SM8450, and enabled
on the HDK board.
On SM8550 GPU, IPA, random number generator, missing SoundWire ports are
added, and enabled on both MTP and QRD devices.
Additionally a large number of smaller functional and DeviceTree binding
validation issues are corrected across a variety of platforms.
* tag 'qcom-arm64-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (288 commits)
arm64: dts: qcom: sc8180x-primus: Allow UFS regulators load/mode setting
arm64: dts: qcom: sc8180x: Describe the GIC redistributor
arm64: dts: qcom: sc8180x: Add interconnects to UFS
arm64: dts: qcom: sc8180x: Add missing MDP clocks
arm64: dts: qcom: sc8180x: Add UFS GDSC
arm64: dts: qcom: sc7280*: move MPSS and WPSS memory to dtsi
arm64: dts: qcom: sc7280: Rename reserved-memory nodes
arm64: dts: qcom: sc7280: Remove unused second MPSS reg
arm64: dts: qcom: sdm670: add display subsystem
arm64: dts: qcom: sm8150-hdk: enable DisplayPort and USB-C altmode
arm64: dts: qcom: sm8150: add USB-C ports to the OTG USB host
arm64: dts: qcom: sm8150: add USB-C ports to the USB+DP QMP PHY
arm64: dts: qcom: sm8150: add DisplayPort controller
arm64: dts: qcom: sm8150-hdk: fix SS USB regulators
arm64: dts: qcom: sm8150-hdk: enable HDMI output
arm64: dts: qcom: sm8150: make dispcc cast minimal vote on MMCX
arm64: dts: qcom: sm8650: add fastrpc-compute-cb nodes
arm64: dts: qcom: sm8550-qrd: add PM8010 regulators
arm64: dts: qcom: sm8550-mtp: Add pm8010 regulators
arm64: dts: qcom: qcm2290: Hook up MPM
...
Link: https://lore.kernel.org/r/20231219145402.874161-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
