Commit graph

6 commits

Author SHA1 Message Date
Ben Skeggs
ebb195dbb3 drm/nouveau/mc: move NV_PMC_ENABLE bashing to chipset-specific code
Ampere needs different handling here, most of what we touch has moved.

We probably want to refactor these interfaces in general, but I'm not
yet sure how they should look, this will get the job done for now.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:36 +10:00
Ben Skeggs
fe76fe497c drm/nouveau/mc: implement intr handling on top of nvkm_intr
- new-style handlers can now be used here too
- decent clean-up

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:36 +10:00
Ben Skeggs
1fc2fddfbc drm/nouveau/mc: switch to instanced constructor
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11 11:49:54 +10:00
Ben Skeggs
94cad89ae4 drm/nouveau/mc/gp10b: make gp10b_mc_init static
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2020-07-24 18:50:46 +10:00
Ben Skeggs
2f68234fb3 drm/nouveau/mc/gp100-: route fault buffer interrupts to FAULT
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Alexandre Courbot
b9a995def6 drm/nouveau/mc: add GP10B support
GP10B's MC is compatible with GP100's, but engines need to be explicitly
put out of ELPG during init.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06 14:39:04 +10:00