Commit graph

80 commits

Author SHA1 Message Date
Ben Skeggs
76b8f81a5b drm/nouveau: improve handling of 64-bit BARs
GPUs exist now with a 64-bit BAR0, which mean that BAR1 and BAR2's
indices (as passed to pci_resource_len() etc) are bumped up by one.

Modify nvkm_device.resource_addr/size() to take an enum instead of
an integer bar index, and take IORESOURCE_MEM_64 into account when
translating to the "raw" bar id.

[airlied: fixup ERR_PTR]
Signed-off-by: Ben Skeggs <bskeggs@nvidia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timur Tabi <ttabi@nvidia.com>
Tested-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2025-05-19 07:14:35 +10:00
Tom Rix
abe3c66f34 drm/nouveau/fifo: set gf100_fifo_nonstall_block_dump storage-class-specifier to static
gcc with W=1 reports
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c:451:1: error:
  no previous prototype for ‘gf100_fifo_nonstall_block’ [-Werror=missing-prototypes]
  451 | gf100_fifo_nonstall_block(struct nvkm_event *event, int type, int index)
      | ^~~~~~~~~~~~~~~~~~~~~~~~~

gf100_fifo_nonstall_block is only used in gf100.c, so it should be static

Signed-off-by: Tom Rix <trix@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230303132731.1919329-1-trix@redhat.com
2023-03-16 14:53:15 +01:00
Ben Skeggs
06db7fded6 drm/nouveau/fifo: add new channel classes
Exposes a bunch of the new features that became possible as a result
of the earlier commits.  DRM will build on this in the future to add
support for features such as SCG ("async compute") and multi-device
rendering, as part of the work necessary to be able to write a half-
decent vulkan driver - finally.

For the moment, this just crudely ports DRM to the API changes.

- channel class interfaces now the same for all HW classes
- channel group class exposed (SCG)
- channel runqueue selector exposed (SCG)
- channel sub-device id control exposed (multi-device rendering)
- channel names in logging will reflect creating process, not fd owner
- explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer
- drm is smarter about determining the appropriate channel class to use

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:50 +10:00
Ben Skeggs
8ab849d6dd drm/nouveau/fifo: add new engine context handling
Builds on the context tracking that was added earlier.

- marks engine context PTEs as 'priv' where possible

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:49 +10:00
Ben Skeggs
3647c53bd7 drm/nouveau/fifo: add RAMFC info to nvkm_chan_func
- adds support for specifying SUBDEVICE_ID for channel
- rounds non-power-of-two GPFIFO sizes down, rather than up

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:49 +10:00
Ben Skeggs
fbe9f4337c drm/nouveau/fifo: add USERD info to nvkm_chan_func
And use it to cleanup multiple implementations of almost the same thing.

- prepares for non-polled / client-provided USERD
- only zeroes relevant "registers", rather than entire USERD

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:49 +10:00
Ben Skeggs
d3e7a4392c drm/nouveau/fifo: add RAMIN info to nvkm_chan_func
Currently provided by {chan,dma,gpfifo}*.c, and those are going away.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:49 +10:00
Ben Skeggs
b084fff210 drm/nouveau/fifo: add common runlist control
- less dependence on waiting for runlist updates, on GPUs that allow it
- supports runqueue selector in RAMRL entries
- completes switch to common runl/cgrp/chan topology info

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:49 +10:00
Ben Skeggs
4d60100a23 drm/nouveau/fifo: add common channel recovery
That sure was fun to untangle.

- handled per-runlist, rather than globally
- more straight-forward process in general
- various potential SW/HW races have been fixed
- fixes lockdep issues that were present in >=gk104's prior implementation
- volta recovery now actually stands a chance of working
- volta/turing waiting for PBDMA idle before engine reset
- turing using hw-provided TSG info for CTXSW_TIMEOUT

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:49 +10:00
Ben Skeggs
520db0405e drm/nouveau/fifo: kill channel on a selection of PBDMA errors
A bunch of these can be handled in such a way that the channel can
continue, however, any of these are a pretty decent sign something
has gone horribly wrong, and the safest option is to disable the
channel.

This is a bit of a hack, we will want to handle these individually
and dump relevant debug info for each at some point.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:49 +10:00
Ben Skeggs
acff941535 drm/nouveau/fifo: add chan/cgrp preempt()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:49 +10:00
Ben Skeggs
67059b9fb8 drm/nouveau/fifo: add chan start()/stop()
- nvkm_chan_error() built on top, stops channel and sends 'killed' event
- removes an odd double-bashing of channel enable regs on kepler and up
- pokes doorbell on turing and up, after enabling channel

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:48 +10:00
Ben Skeggs
62742b5ef3 drm/nouveau/fifo: add chan bind()/unbind()
- stops programming (non-existent) runl id field on bind(), from maxwell

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:48 +10:00
Ben Skeggs
3a6bc9c242 drm/nouveau/fifo: add runlist block()/allow()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:48 +10:00
Ben Skeggs
4a492fd5d2 drm/nouveau/fifo: add runlist wait()
- adds g8x/turing registers, which were missing before
- switches fermi to polled wait, like later hw (see: 4f2fc25c0f8bc...)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:48 +10:00
Ben Skeggs
c358f53871 drm/nouveau/fifo: add new channel lookup interfaces
- supports per-runlist CHIDs
- channel group lock held across reference, rather than global lock

v2:
- remove unnecessary parenthesis

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:48 +10:00
Ben Skeggs
e43c872c03 drm/nouveau/fifo: merge mmu fault handlers together
After updating GF100 implementation from the GK104/TU102 ones, and using
the new runlist/engine topology info, all three handlers become (almost)
identical.

- there's a temporary kludge to call through to the HW-specific recovery
- engine fault mapping info determined at load time, not on every fault

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:48 +10:00
Ben Skeggs
923f1ff527 drm/nouveau/fifo: move PBDMA intr to runq
- merges gf100/gk104- NV_PFIFO_INTR_0_PBDMA and NV_PPBDMA_INTR_0 code

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:48 +10:00
Ben Skeggs
87c8602431 drm/nouveau/fifo: move PBDMA init to runq
- bumps pbdma timeout to value RM uses on newer HW
- bumps fb timeout to max from boot default
- one/both of these greatly improves stability on // piglit runs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:48 +10:00
Ben Skeggs
324176e7c8 drm/nouveau/fifo: program NV_PFIFO_FB_TIMEOUT on init
NVGPU and RM both program this value.

Fixes a bunch of random hangs running parallel piglit.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2022-11-09 10:44:48 +10:00
Ben Skeggs
965c41d911 drm/nouveau/fifo: tidy global PBDMA init
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2022-11-09 10:44:48 +10:00
Ben Skeggs
d67f3b9646 drm/nouveau/fifo: tidy up non-stall intr handling
- removes a layer of indirection in the intr handling
- prevents non-stall ctrl racing with unknown intrs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:47 +10:00
Ben Skeggs
2fc71a0566 drm/nouveau/fifo: use explicit intr interfaces
More control, and shallower call-chain to get to the point.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:47 +10:00
Ben Skeggs
0fc72ee9d8 drm/nouveau/fifo: use runlist engine info to lookup engine classes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:47 +10:00
Ben Skeggs
d94470e9d1 drm/nouveau/fifo: add common runlist/engine topology
Creates an nvkm_runl for each runlist on the GPU, and an nvkm_engn for
each engine that is reachable from a runlist.

- basically what gk104- already does, but extended to all chips
- adds per-runlist CHID allocators (Ampere)
- splits g98/gt2xx out from g84 (different target engines)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:47 +10:00
Ben Skeggs
1c488ba96e drm/nouveau/fifo: add runq
Creates an nvkm_runq for each PBDMA, these will be associated with the
relevant runlist(s) later.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:47 +10:00
Ben Skeggs
800ac1f8d7 drm/nouveau/fifo: add chid allocator
We need to be able to allocate TSG IDs as well as channel IDs, also,
Ampere has per-runlist channel IDs.

- holds per-ID private data, which will be used for/to protect lookup
- holds an nvkm_event which will be used for events tied to IDs
- not used yet beyond setup, and switching use of "fifo->nr - 1" for
  channel ID mask to "chid->mask"

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:47 +10:00
Ben Skeggs
9be9c606c4 drm/nouveau/fifo: merge gk104_fifo_func into nvkm_host_func
This makes it easier to transition everything.

- a couple of function renames for collisions

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:47 +10:00
Ben Skeggs
fd67738a28 drm/nouveau/fifo: pre-move some blocks of code around
- will make subsequent patches more obvious
- no code changes

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:47 +10:00
Ben Skeggs
f5e4568991 drm/nouveau/fifo: unify handling of channel classes
Adds the basic skeleton for common channel (group) interfaces.

- common behaviour between <gk104 and >=gk104 impl's
- separates priv/user channel objects
- passthrough to existing object for now, kludges removed later

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:46 +10:00
Ben Skeggs
8c18138c76 drm/nouveau/fifo: add chid_nr()
- reads channel count from GPU from gm200 onwards
- removes gm20b/gp10b (they become identical to gm200/gp100)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2022-11-09 10:44:46 +10:00
Ben Skeggs
088bfe43f0 drm/nouveau/fifo/gf100-: switch static mmu fault id list to type+inst
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11 11:49:57 +10:00
Ben Skeggs
c6198d3465 drm/nouveau/fifo/gf100: use fifo engine id for engine recovery mask
Instead of subdev index.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11 11:49:57 +10:00
Ben Skeggs
496162037c drm/nouveau/fifo: add id_engine hook
Will be used by common code in subsequent commits to lookup driver
engine state from HW engine ID.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11 11:49:57 +10:00
Ben Skeggs
64f7c698be drm/nouveau/fifo: add engine_id hook
Will be used by common code in subsequent commits to replace arrays
indexed by subdev index.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11 11:49:56 +10:00
Ben Skeggs
ab0db2bd85 drm/nouveau/fifo: switch to instanced constructor
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11 11:49:56 +10:00
Ben Skeggs
efe2a9eccd drm/nouveau/device: pass instance id when looking up a subdev/engine
This switches to using the subdev list for lookup, and otherwise should
be a no-op aside from switching the function signatures.

Callers will be transitioned to split type+inst individually.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11 10:14:32 +10:00
Ben Skeggs
9c28abb7db drm/nouveau/subdev: store full subdev name in struct
Much easier to store this to avoid having to reconstruct a string for a
specific subdev, taking into account whether it's instanced or not.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11 10:14:26 +10:00
Ben Skeggs
a641936065 drm/nouveau/fifo: private mutex
nvkm_subdev.mutex is going away.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2021-02-11 10:14:20 +10:00
Ben Skeggs
cf9518b50a drm/nouveau/fifo/gf1xx: convert to using nvkm_fault_data
Would like to be able to reuse gf100_fifo_intr_fault() for (some of) the
later chipsets too, as it's identical.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2019-08-23 12:55:32 +10:00
Ben Skeggs
302daab1a7 drm/nouveau/fifo/gf100-: call into BAR to reset BARs after MMU fault
This is needed for Turing, but we're supposed to wait for completion after
re-writing the value on older GPUs anyway.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11 15:37:47 +10:00
Ben Skeggs
01f349fcad drm/nouveau/fifo/gf100-: use new interfaces for vmm operations
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:31 +10:00
Ben Skeggs
997a89003c drm/nouveau/core/memory: add reference counting
We need to be able to prevent memory from being freed while it's still
mapped in a GPU's address-space.

Will be used by upcoming MMU changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:22 +10:00
Ben Skeggs
19a82e492c drm/nouveau/core/memory: change map interface to support upcoming mmu changes
Map flags (access, kind, etc) are currently defined in either the VMA,
or the memory object, which turns out to not be ideal for things like
suballocated buffers, etc.

These will become per-map flags instead, so we need to support passing
these arguments in nvkm_memory_map().

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:22 +10:00
Ben Skeggs
570889dc50 drm/nouveau/bar: modify interface to bar1 vmm mapping
Upcoming changes will remove the nvkm_vmm pointer from nvkm_vma, instead
requiring it to be explicitly specified on each operation.

It's not currently possible to get this information for BAR1 mappings,
so let's fix that ahead of time.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-11-02 13:32:18 +10:00
Ben Skeggs
ff9f29abf0 drm/nouveau/fifo/gf100-: provide notification to user if channel is killed
There are instances (such as non-recoverable GPU page faults) where
NVKM decides that a channel's context is no longer viable, and will
be removed from the runlist.

This commit notifies the owner of the channel when this happens, so
it has the opportunity to take some kind of recovery action instead
of hanging.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 17:38:08 +10:00
Ben Skeggs
d2ee360564 drm/nouveau/core/memory: distinguish between coherent/non-coherent targets
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-02-17 15:15:01 +10:00
Ben Skeggs
ec884f74f1 drm/nouveau/fifo/gf100-: recover from host mmu faults
This has been on the TODO list for a while now, recovering from things
such as attempting to execute a push buffer or touch a semaphore in an
unmapped memory area.

The only thing required on the HW side here is that the offending
channel is removed from the runlist, and *not* a full reset of PFIFO.

This used to be a bit messier to handle before the rework to make use
of engine topology info, but is apparently now trivial.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-12-13 11:38:51 +10:00
Ben Skeggs
1015d81122 drm/nouveau/fifo/gf100: fix certain engines not being recovered after a fault
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:38 +10:00
Ben Skeggs
f22d7d45fa drm/nouveau/fifo/gf100: don't attempt recovery of unknown mmu engines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:38 +10:00