Move properties from SoM's dtsi to carrierboard's dts as they are
actually defined by the carrier board design.
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
RV-3028 RTC can be used to wakeup the system on phyGATE-Tauri-L-i.MX8MM,
mark the device as wakeup source.
Signed-off-by: Andrej Picej <andrej.picej@norik.com>
Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
I210 intel ethernet controller is connected to PCIe. Enable the PHY
to use the ethernet controller.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Since commit 26c9d152eb ("dt-bindings: tpm: Consolidate TCG TIS
bindings"), several issues are reported by "make dtbs_check" for arm64
devicetrees:
The compatible property needs to contain the chip's name in addition to
the generic "tcg,tpm_tis-spi" and the nodename needs to be "tpm@0"
rather than "cr50@0":
tpm@1: compatible: ['tcg,tpm_tis-spi'] is too short
from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml#
cr50@0: $nodename:0: 'cr50@0' does not match '^tpm(@[0-9a-f]+)?$'
from schema $id: http://devicetree.org/schemas/tpm/google,cr50.yaml#
Fix these schema violations.
phyGATE-Tauri uses an Infineon SLB9670:
https://lore.kernel.org/all/ab45c82485fa272f74adf560cbb58ee60cc42689.camel@phytec.de/
Gateworks Venice uses an Atmel ATTPM20P:
https://trac.gateworks.com/wiki/tpm
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
phyGATE-Tauri uses a phyCORE-i.MX8MM SoM. Add device tree for the board.
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
