mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-18 12:30:31 +00:00
crypto: tegra - Fix HASH intermediate result handling
The intermediate hash values generated during an update task were
handled incorrectly in the driver. The values have a defined format for
each algorithm. Copying and pasting from the HASH_RESULT register
balantly would not work for all the supported algorithms. This incorrect
handling causes failures when there is a context switch between multiple
operations.
To handle the expected format correctly, add a separate buffer for
storing the intermediate results for each request. Remove the previous
copy/paste functions which read/wrote to the registers directly. Instead
configure the hardware to get the intermediate result copied to the
buffer and use host1x path to restore the intermediate hash results.
Fixes: 0880bb3b00 ("crypto: tegra - Add Tegra Security Engine driver")
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Akhil R
Herbert Xu
parent
97ee15ea10
commit
ff4b7df0b5
2 changed files with 98 additions and 52 deletions
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@ -34,6 +34,7 @@ struct tegra_sha_reqctx {
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struct tegra_se_datbuf datbuf;
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struct tegra_se_datbuf residue;
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struct tegra_se_datbuf digest;
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struct tegra_se_datbuf intr_res;
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unsigned int alg;
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unsigned int config;
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unsigned int total_len;
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@ -211,9 +212,62 @@ static int tegra_sha_fallback_export(struct ahash_request *req, void *out)
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return crypto_ahash_export(&rctx->fallback_req, out);
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}
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static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr,
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static int tegra_se_insert_hash_result(struct tegra_sha_ctx *ctx, u32 *cpuvaddr,
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struct tegra_sha_reqctx *rctx)
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{
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__be32 *res_be = (__be32 *)rctx->intr_res.buf;
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u32 *res = (u32 *)rctx->intr_res.buf;
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int i = 0, j;
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cpuvaddr[i++] = 0;
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cpuvaddr[i++] = host1x_opcode_setpayload(HASH_RESULT_REG_COUNT);
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cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_HASH_RESULT);
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for (j = 0; j < HASH_RESULT_REG_COUNT; j++) {
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int idx = j;
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/*
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* The initial, intermediate and final hash value of SHA-384, SHA-512
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* in SHA_HASH_RESULT registers follow the below layout of bytes.
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*
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* +---------------+------------+
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* | HASH_RESULT_0 | B4...B7 |
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* +---------------+------------+
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* | HASH_RESULT_1 | B0...B3 |
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* +---------------+------------+
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* | HASH_RESULT_2 | B12...B15 |
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* +---------------+------------+
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* | HASH_RESULT_3 | B8...B11 |
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* +---------------+------------+
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* | ...... |
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* +---------------+------------+
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* | HASH_RESULT_14| B60...B63 |
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* +---------------+------------+
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* | HASH_RESULT_15| B56...B59 |
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* +---------------+------------+
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*
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*/
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if (ctx->alg == SE_ALG_SHA384 || ctx->alg == SE_ALG_SHA512)
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idx = (j % 2) ? j - 1 : j + 1;
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/* For SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 the initial
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* intermediate and final hash value when stored in
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* SHA_HASH_RESULT registers, the byte order is NOT in
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* little-endian.
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*/
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if (ctx->alg <= SE_ALG_SHA512)
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cpuvaddr[i++] = be32_to_cpu(res_be[idx]);
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else
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cpuvaddr[i++] = res[idx];
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}
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return i;
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}
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static int tegra_sha_prep_cmd(struct tegra_sha_ctx *ctx, u32 *cpuvaddr,
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struct tegra_sha_reqctx *rctx)
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{
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struct tegra_se *se = ctx->se;
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u64 msg_len, msg_left;
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int i = 0;
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@ -241,7 +295,7 @@ static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr,
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cpuvaddr[i++] = upper_32_bits(msg_left);
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cpuvaddr[i++] = 0;
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cpuvaddr[i++] = 0;
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cpuvaddr[i++] = host1x_opcode_setpayload(6);
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cpuvaddr[i++] = host1x_opcode_setpayload(2);
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cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_CFG);
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cpuvaddr[i++] = rctx->config;
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@ -249,15 +303,29 @@ static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr,
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cpuvaddr[i++] = SE_SHA_TASK_HASH_INIT;
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rctx->task &= ~SHA_FIRST;
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} else {
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cpuvaddr[i++] = 0;
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/*
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* If it isn't the first task, program the HASH_RESULT register
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* with the intermediate result from the previous task
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*/
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i += tegra_se_insert_hash_result(ctx, cpuvaddr + i, rctx);
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}
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cpuvaddr[i++] = host1x_opcode_setpayload(4);
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cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_IN_ADDR);
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cpuvaddr[i++] = rctx->datbuf.addr;
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cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->datbuf.addr)) |
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SE_ADDR_HI_SZ(rctx->datbuf.size));
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cpuvaddr[i++] = rctx->digest.addr;
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cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->digest.addr)) |
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SE_ADDR_HI_SZ(rctx->digest.size));
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if (rctx->task & SHA_UPDATE) {
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cpuvaddr[i++] = rctx->intr_res.addr;
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cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->intr_res.addr)) |
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SE_ADDR_HI_SZ(rctx->intr_res.size));
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} else {
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cpuvaddr[i++] = rctx->digest.addr;
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cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->digest.addr)) |
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SE_ADDR_HI_SZ(rctx->digest.size));
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}
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if (rctx->key_id) {
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cpuvaddr[i++] = host1x_opcode_setpayload(1);
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cpuvaddr[i++] = se_host1x_opcode_nonincr_w(SE_SHA_CRYPTO_CFG);
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@ -266,36 +334,18 @@ static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr,
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cpuvaddr[i++] = host1x_opcode_setpayload(1);
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cpuvaddr[i++] = se_host1x_opcode_nonincr_w(SE_SHA_OPERATION);
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cpuvaddr[i++] = SE_SHA_OP_WRSTALL |
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SE_SHA_OP_START |
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cpuvaddr[i++] = SE_SHA_OP_WRSTALL | SE_SHA_OP_START |
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SE_SHA_OP_LASTBUF;
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cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
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cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
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host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
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dev_dbg(se->dev, "msg len %llu msg left %llu cfg %#x",
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msg_len, msg_left, rctx->config);
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dev_dbg(se->dev, "msg len %llu msg left %llu sz %lu cfg %#x",
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msg_len, msg_left, rctx->datbuf.size, rctx->config);
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return i;
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}
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static void tegra_sha_copy_hash_result(struct tegra_se *se, struct tegra_sha_reqctx *rctx)
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{
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int i;
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for (i = 0; i < HASH_RESULT_REG_COUNT; i++)
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rctx->result[i] = readl(se->base + se->hw->regs->result + (i * 4));
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}
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static void tegra_sha_paste_hash_result(struct tegra_se *se, struct tegra_sha_reqctx *rctx)
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{
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int i;
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for (i = 0; i < HASH_RESULT_REG_COUNT; i++)
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writel(rctx->result[i],
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se->base + se->hw->regs->result + (i * 4));
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}
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static int tegra_sha_do_init(struct ahash_request *req)
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{
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struct tegra_sha_reqctx *rctx = ahash_request_ctx(req);
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@ -325,8 +375,17 @@ static int tegra_sha_do_init(struct ahash_request *req)
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if (!rctx->residue.buf)
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goto resbuf_fail;
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rctx->intr_res.size = HASH_RESULT_REG_COUNT * 4;
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rctx->intr_res.buf = dma_alloc_coherent(se->dev, rctx->intr_res.size,
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&rctx->intr_res.addr, GFP_KERNEL);
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if (!rctx->intr_res.buf)
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goto intr_res_fail;
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return 0;
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intr_res_fail:
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dma_free_coherent(se->dev, rctx->residue.size, rctx->residue.buf,
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rctx->residue.addr);
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resbuf_fail:
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dma_free_coherent(se->dev, rctx->digest.size, rctx->digest.buf,
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rctx->digest.addr);
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@ -356,7 +415,6 @@ static int tegra_sha_do_update(struct ahash_request *req)
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rctx->src_sg = req->src;
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rctx->datbuf.size = (req->nbytes + rctx->residue.size) - nresidue;
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rctx->total_len += rctx->datbuf.size;
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/*
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* If nbytes are less than a block size, copy it residue and
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@ -365,12 +423,12 @@ static int tegra_sha_do_update(struct ahash_request *req)
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if (nblks < 1) {
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scatterwalk_map_and_copy(rctx->residue.buf + rctx->residue.size,
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rctx->src_sg, 0, req->nbytes, 0);
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rctx->residue.size += req->nbytes;
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return 0;
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}
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rctx->datbuf.buf = dma_alloc_coherent(ctx->se->dev, rctx->datbuf.size,
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rctx->datbuf.buf = dma_alloc_coherent(se->dev, rctx->datbuf.size,
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&rctx->datbuf.addr, GFP_KERNEL);
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if (!rctx->datbuf.buf)
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return -ENOMEM;
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@ -387,31 +445,15 @@ static int tegra_sha_do_update(struct ahash_request *req)
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/* Update residue value with the residue after current block */
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rctx->residue.size = nresidue;
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rctx->total_len += rctx->datbuf.size;
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rctx->config = tegra_sha_get_config(rctx->alg) |
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SE_SHA_DST_HASH_REG;
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/*
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* If this is not the first 'update' call, paste the previous copied
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* intermediate results to the registers so that it gets picked up.
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* This is to support the import/export functionality.
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*/
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if (!(rctx->task & SHA_FIRST))
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tegra_sha_paste_hash_result(se, rctx);
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size = tegra_sha_prep_cmd(se, cpuvaddr, rctx);
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SE_SHA_DST_MEMORY;
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size = tegra_sha_prep_cmd(ctx, cpuvaddr, rctx);
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ret = tegra_se_host1x_submit(se, se->cmdbuf, size);
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/*
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* If this is not the final update, copy the intermediate results
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* from the registers so that it can be used in the next 'update'
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* call. This is to support the import/export functionality.
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*/
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if (!(rctx->task & SHA_FINAL))
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tegra_sha_copy_hash_result(se, rctx);
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dma_free_coherent(ctx->se->dev, rctx->datbuf.size,
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dma_free_coherent(se->dev, rctx->datbuf.size,
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rctx->datbuf.buf, rctx->datbuf.addr);
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return ret;
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@ -443,8 +485,7 @@ static int tegra_sha_do_final(struct ahash_request *req)
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rctx->config = tegra_sha_get_config(rctx->alg) |
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SE_SHA_DST_MEMORY;
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size = tegra_sha_prep_cmd(se, cpuvaddr, rctx);
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size = tegra_sha_prep_cmd(ctx, cpuvaddr, rctx);
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ret = tegra_se_host1x_submit(se, se->cmdbuf, size);
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if (ret)
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goto out;
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@ -461,6 +502,10 @@ out_free:
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rctx->residue.buf, rctx->residue.addr);
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dma_free_coherent(se->dev, rctx->digest.size, rctx->digest.buf,
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rctx->digest.addr);
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dma_free_coherent(se->dev, rctx->intr_res.size, rctx->intr_res.buf,
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rctx->intr_res.addr);
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return ret;
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}
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@ -24,6 +24,7 @@
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#define SE_STREAM_ID 0x90
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#define SE_SHA_CFG 0x4004
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#define SE_SHA_IN_ADDR 0x400c
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#define SE_SHA_KEY_ADDR 0x4094
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#define SE_SHA_KEY_DATA 0x4098
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#define SE_SHA_KEYMANIFEST 0x409c
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