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net: stmmac: dwmac-qcom-ethqos: add support for the phyaux clock
On sa8775p, the EMAC revision is 4 and we use SGMII instead of RGMII. There's no "rgmii" clock but there's a fourth clock under a different name: "phyaux". Add a new field to the chip data struct that specifies the link clock name. Default to "rgmii" for backward compatibility. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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parent
0dec3b48aa
commit
feeb27165c
1 changed files with 16 additions and 15 deletions
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@ -85,6 +85,7 @@ struct ethqos_emac_driver_data {
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unsigned int num_por;
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bool rgmii_config_loopback_en;
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bool has_emac3;
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const char *link_clk_name;
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struct dwmac4_addrs dwmac4_addrs;
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};
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@ -92,8 +93,8 @@ struct qcom_ethqos {
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struct platform_device *pdev;
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void __iomem *rgmii_base;
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unsigned int rgmii_clk_rate;
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struct clk *rgmii_clk;
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unsigned int link_clk_rate;
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struct clk *link_clk;
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struct phy *serdes_phy;
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unsigned int speed;
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@ -156,23 +157,23 @@ static void rgmii_dump(void *priv)
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#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL)
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static void
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ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed)
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ethqos_update_link_clk(struct qcom_ethqos *ethqos, unsigned int speed)
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{
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switch (speed) {
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case SPEED_1000:
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ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ;
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ethqos->link_clk_rate = RGMII_1000_NOM_CLK_FREQ;
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break;
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case SPEED_100:
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ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
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ethqos->link_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
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break;
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case SPEED_10:
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ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
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ethqos->link_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
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break;
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}
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clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate);
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clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
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}
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static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
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@ -563,7 +564,7 @@ static void ethqos_fix_mac_speed(void *priv, unsigned int speed)
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struct qcom_ethqos *ethqos = priv;
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ethqos->speed = speed;
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ethqos_update_rgmii_clk(ethqos, speed);
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ethqos_update_link_clk(ethqos, speed);
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ethqos_configure(ethqos);
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}
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@ -597,9 +598,9 @@ static int ethqos_clks_config(void *priv, bool enabled)
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int ret = 0;
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if (enabled) {
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ret = clk_prepare_enable(ethqos->rgmii_clk);
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ret = clk_prepare_enable(ethqos->link_clk);
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if (ret) {
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dev_err(ðqos->pdev->dev, "rgmii_clk enable failed\n");
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dev_err(ðqos->pdev->dev, "link_clk enable failed\n");
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return ret;
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}
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@ -610,7 +611,7 @@ static int ethqos_clks_config(void *priv, bool enabled)
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*/
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ethqos_set_func_clk_en(ethqos);
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} else {
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clk_disable_unprepare(ethqos->rgmii_clk);
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clk_disable_unprepare(ethqos->link_clk);
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}
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return ret;
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@ -662,9 +663,9 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
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ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
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ethqos->has_emac3 = data->has_emac3;
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ethqos->rgmii_clk = devm_clk_get(dev, "rgmii");
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if (IS_ERR(ethqos->rgmii_clk)) {
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ret = PTR_ERR(ethqos->rgmii_clk);
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ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");
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if (IS_ERR(ethqos->link_clk)) {
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ret = PTR_ERR(ethqos->link_clk);
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goto out_config_dt;
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}
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@ -683,7 +684,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
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}
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ethqos->speed = SPEED_1000;
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ethqos_update_rgmii_clk(ethqos, SPEED_1000);
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ethqos_update_link_clk(ethqos, SPEED_1000);
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ethqos_set_func_clk_en(ethqos);
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plat_dat->bsp_priv = ethqos;
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