From a268b155100b37cd280fcfd3ef72be536f33dfa0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sat, 29 Jan 2022 12:52:20 +0100 Subject: [PATCH 1/8] dt-bindings: arm/npcm: Add binding for global control registers (GCR) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A nuvoton,*-gcr node is present in nuvoton-common-npcm7xx.dtsi and will be added to nuvoton-wpcm450.dtsi. It is necessary for the NPCM7xx and WPCM450 pinctrl drivers, and may later be used to retrieve SoC model and version information. This patch adds a binding to describe this node. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20220129115228.2257310-2-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley --- .../bindings/arm/npcm/nuvoton,gcr.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml new file mode 100644 index 000000000000..fcb211add7d3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Global Control Registers block in Nuvoton SoCs + +maintainers: + - Jonathan Neuschäfer + +description: + The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs + that expose misc functionality such as chip model and version information or + pinmux settings. + +properties: + compatible: + items: + - enum: + - nuvoton,wpcm450-gcr + - nuvoton,npcm750-gcr + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + gcr: syscon@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0x800000 0x1000>; + + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x38 0x07>; + idle-states = <2>; + }; + }; From 2e26d833c6d7f341b0d3038cb8b740fa5625fe88 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sat, 29 Jan 2022 12:52:21 +0100 Subject: [PATCH 2/8] MAINTAINERS: Match all of bindings/arm/npcm/ as part of NPCM architecture MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All files in Documentation/devicetree/bindings/arm/npcm/ belong to the Nuvoton NPCM architecture, even when their names might not spell it out explicitly. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220129115228.2257310-3-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index ea3e6c914384..d84dde42e33d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2363,6 +2363,7 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Supported F: Documentation/devicetree/bindings/*/*/*npcm* F: Documentation/devicetree/bindings/*/*npcm* +F: Documentation/devicetree/bindings/arm/npcm/* F: arch/arm/boot/dts/nuvoton-npcm* F: arch/arm/mach-npcm/ F: drivers/*/*npcm* From f14a58097eec1e7e52a769ff6cbbb8845c2f0781 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sat, 29 Jan 2022 12:52:22 +0100 Subject: [PATCH 3/8] ARM: dts: wpcm450: Add global control registers (GCR) node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs that expose misc functionality such as chip model and version information or pinmux settings. This patch adds a GCR node to nuvoton-wpcm450.dtsi in preparation for enabling pinctrl on this SoC. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220129115228.2257310-4-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index d7cbeb187484..a17ee70085dd 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -33,6 +33,11 @@ interrupt-parent = <&aic>; ranges; + gcr: syscon@b0000000 { + compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd"; + reg = <0xb0000000 0x200>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; From 733bc2f432cfecba8a6661989878fd0d59e9c970 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sat, 29 Jan 2022 12:52:25 +0100 Subject: [PATCH 4/8] ARM: dts: wpcm450: Add pinctrl and GPIO nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds the pin controller and GPIO banks to the devicetree for the WPCM450 SoC. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20220129115228.2257310-7-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 72 ++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index a17ee70085dd..66c35626c80a 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -8,6 +8,17 @@ #address-cells = <1>; #size-cells = <1>; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -77,5 +88,66 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0: gpio@0 { + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>, + <4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + + gpio1: gpio@1 { + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + + gpio2: gpio@2 { + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@3 { + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio4: gpio@4 { + reg = <4>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio5: gpio@5 { + reg = <5>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio6: gpio@6 { + reg = <6>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio7: gpio@7 { + reg = <7>; + gpio-controller; + #gpio-cells = <2>; + }; + }; }; }; From 871e181bb4fdec4a834dc8a529d83ee7b7be31d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sat, 29 Jan 2022 12:52:26 +0100 Subject: [PATCH 5/8] ARM: dts: wpcm450: Add pin functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As done in nuvoton-common-npcm7xx.dtsi, this patch adds pinmux nodes for all pin functions to nuvoton-wpcm450.dtsi. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220129115228.2257310-8-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 305 +++++++++++++++++++++++++ 1 file changed, 305 insertions(+) diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 66c35626c80a..0c547bd88bdb 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -148,6 +148,311 @@ gpio-controller; #gpio-cells = <2>; }; + + smb3_pins: mux-smb3 { + groups = "smb3"; + function = "smb3"; + }; + + smb4_pins: mux-smb4 { + groups = "smb4"; + function = "smb4"; + }; + + smb5_pins: mux-smb5 { + groups = "smb5"; + function = "smb5"; + }; + + scs1_pins: mux-scs1 { + groups = "scs1"; + function = "scs1"; + }; + + scs2_pins: mux-scs2 { + groups = "scs2"; + function = "scs2"; + }; + + scs3_pins: mux-scs3 { + groups = "scs3"; + function = "scs3"; + }; + + smb0_pins: mux-smb0 { + groups = "smb0"; + function = "smb0"; + }; + + smb1_pins: mux-smb1 { + groups = "smb1"; + function = "smb1"; + }; + + smb2_pins: mux-smb2 { + groups = "smb2"; + function = "smb2"; + }; + + bsp_pins: mux-bsp { + groups = "bsp"; + function = "bsp"; + }; + + hsp1_pins: mux-hsp1 { + groups = "hsp1"; + function = "hsp1"; + }; + + hsp2_pins: mux-hsp2 { + groups = "hsp2"; + function = "hsp2"; + }; + + r1err_pins: mux-r1err { + groups = "r1err"; + function = "r1err"; + }; + + r1md_pins: mux-r1md { + groups = "r1md"; + function = "r1md"; + }; + + rmii2_pins: mux-rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + r2err_pins: mux-r2err { + groups = "r2err"; + function = "r2err"; + }; + + r2md_pins: mux-r2md { + groups = "r2md"; + function = "r2md"; + }; + + kbcc_pins: mux-kbcc { + groups = "kbcc"; + function = "kbcc"; + }; + + dvo0_pins: mux-dvo0 { + groups = "dvo"; + function = "dvo0"; + }; + + dvo3_pins: mux-dvo3 { + groups = "dvo"; + function = "dvo3"; + }; + + clko_pins: mux-clko { + groups = "clko"; + function = "clko"; + }; + + smi_pins: mux-smi { + groups = "smi"; + function = "smi"; + }; + + uinc_pins: mux-uinc { + groups = "uinc"; + function = "uinc"; + }; + + gspi_pins: mux-gspi { + groups = "gspi"; + function = "gspi"; + }; + + mben_pins: mux-mben { + groups = "mben"; + function = "mben"; + }; + + xcs2_pins: mux-xcs2 { + groups = "xcs2"; + function = "xcs2"; + }; + + xcs1_pins: mux-xcs1 { + groups = "xcs1"; + function = "xcs1"; + }; + + sdio_pins: mux-sdio { + groups = "sdio"; + function = "sdio"; + }; + + sspi_pins: mux-sspi { + groups = "sspi"; + function = "sspi"; + }; + + fi0_pins: mux-fi0 { + groups = "fi0"; + function = "fi0"; + }; + + fi1_pins: mux-fi1 { + groups = "fi1"; + function = "fi1"; + }; + + fi2_pins: mux-fi2 { + groups = "fi2"; + function = "fi2"; + }; + + fi3_pins: mux-fi3 { + groups = "fi3"; + function = "fi3"; + }; + + fi4_pins: mux-fi4 { + groups = "fi4"; + function = "fi4"; + }; + + fi5_pins: mux-fi5 { + groups = "fi5"; + function = "fi5"; + }; + + fi6_pins: mux-fi6 { + groups = "fi6"; + function = "fi6"; + }; + + fi7_pins: mux-fi7 { + groups = "fi7"; + function = "fi7"; + }; + + fi8_pins: mux-fi8 { + groups = "fi8"; + function = "fi8"; + }; + + fi9_pins: mux-fi9 { + groups = "fi9"; + function = "fi9"; + }; + + fi10_pins: mux-fi10 { + groups = "fi10"; + function = "fi10"; + }; + + fi11_pins: mux-fi11 { + groups = "fi11"; + function = "fi11"; + }; + + fi12_pins: mux-fi12 { + groups = "fi12"; + function = "fi12"; + }; + + fi13_pins: mux-fi13 { + groups = "fi13"; + function = "fi13"; + }; + + fi14_pins: mux-fi14 { + groups = "fi14"; + function = "fi14"; + }; + + fi15_pins: mux-fi15 { + groups = "fi15"; + function = "fi15"; + }; + + pwm0_pins: mux-pwm0 { + groups = "pwm0"; + function = "pwm0"; + }; + + pwm1_pins: mux-pwm1 { + groups = "pwm1"; + function = "pwm1"; + }; + + pwm2_pins: mux-pwm2 { + groups = "pwm2"; + function = "pwm2"; + }; + + pwm3_pins: mux-pwm3 { + groups = "pwm3"; + function = "pwm3"; + }; + + pwm4_pins: mux-pwm4 { + groups = "pwm4"; + function = "pwm4"; + }; + + pwm5_pins: mux-pwm5 { + groups = "pwm5"; + function = "pwm5"; + }; + + pwm6_pins: mux-pwm6 { + groups = "pwm6"; + function = "pwm6"; + }; + + pwm7_pins: mux-pwm7 { + groups = "pwm7"; + function = "pwm7"; + }; + + hg0_pins: mux-hg0 { + groups = "hg0"; + function = "hg0"; + }; + + hg1_pins: mux-hg1 { + groups = "hg1"; + function = "hg1"; + }; + + hg2_pins: mux-hg2 { + groups = "hg2"; + function = "hg2"; + }; + + hg3_pins: mux-hg3 { + groups = "hg3"; + function = "hg3"; + }; + + hg4_pins: mux-hg4 { + groups = "hg4"; + function = "hg4"; + }; + + hg5_pins: mux-hg5 { + groups = "hg5"; + function = "hg5"; + }; + + hg6_pins: mux-hg6 { + groups = "hg6"; + function = "hg6"; + }; + + hg7_pins: mux-hg7 { + groups = "hg7"; + function = "hg7"; + }; }; }; }; From 706c4fec115db534b2c97e5cdb9762ec3ffc2937 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sat, 29 Jan 2022 12:52:27 +0100 Subject: [PATCH 6/8] ARM: dts: wpcm450-supermicro-x9sci-ln4f: Add GPIO LEDs and buttons MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Supermicro X9SCi-LN4F server mainboard has a two LEDs and a button under the control of the BMC. This patch makes them accessible under Linux running on the BMC. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220129115228.2257310-9-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley --- .../nuvoton-wpcm450-supermicro-x9sci-ln4f.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts index 83f27fbf4e93..3ee61251a16d 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts +++ b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts @@ -8,6 +8,9 @@ #include "nuvoton-wpcm450.dtsi" +#include +#include + / { model = "Supermicro X9SCi-LN4F BMC"; compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450"; @@ -20,6 +23,46 @@ device_type = "memory"; reg = <0 0x08000000>; /* 128 MiB */ }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins>; + + uid { + label = "UID button"; + linux,code = ; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + uid { + label = "UID"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + heartbeat { + label = "heartbeat"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pinctrl { + key_pins: mux-keys { + groups = "gspi", "sspi"; + function = "gpio"; + }; + + led_pins: mux-leds { + groups = "hg3", "hg0", "pwm4"; + function = "gpio"; + }; }; &serial0 { From e6cb1fc9635fcf14dc86a50cacc89c556dbee56c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sat, 29 Jan 2022 12:52:28 +0100 Subject: [PATCH 7/8] ARM: dts: wpcm450: Add pinmux information to UART0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit UART0 always uses the same pins, so lets add the pinctrl information to the common devicetree for WPCM450. UART1 has different connection options, so I'm not adding the pinctrl properties there. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220129115228.2257310-10-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 0c547bd88bdb..93595850a4c3 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -55,6 +55,8 @@ reg-shift = <2>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk24m>; + pinctrl-names = "default"; + pinctrl-0 = <&bsp_pins>; status = "disabled"; }; From 43fd3d4d95cee85e187e5c4ef1d991f77d4d928c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 18 Feb 2022 17:08:34 +0100 Subject: [PATCH 8/8] MAINTAINERS: ARM/WPCM450: Add 'W:' line with wiki MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The wiki is a useful source of 3rd-party information about the SoC, mostly hardware documentation. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20220218160834.320200-1-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d84dde42e33d..e1f92b94e8e6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2374,6 +2374,7 @@ ARM/NUVOTON WPCM450 ARCHITECTURE M: Jonathan Neuschäfer L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Maintained +W: https://github.com/neuschaefer/wpcm450/wiki F: Documentation/devicetree/bindings/*/*wpcm* F: arch/arm/boot/dts/nuvoton-wpcm450* F: arch/arm/mach-npcm/wpcm450.c