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iio: accel: adxl345: complete the list of defines

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Having interrupts events and FIFO available allows to evaluate the
sensor events. Cover the list of interrupt based sensor events. Keep
them in the header file for readability.

Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Link: https://patch.msgid.link/20241228232949.72487-5-l.rubusch@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Lothar Rubusch 2024-12-28 23:29:49 +00:00 • committed by Jonathan Cameron
parent cf04212d1f
commit f9eb057181
1 changed files with 48 additions and 6 deletions
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54
drivers/iio/accel/adxl345.h
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@ -9,10 +9,35 @@
#define _ADXL345_H_
#define ADXL345_REG_DEVID 0x00
#define ADXL345_REG_THRESH_TAP 0x1D
#define ADXL345_REG_OFSX 0x1E
#define ADXL345_REG_OFSY 0x1F
#define ADXL345_REG_OFSZ 0x20
#define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index))
/* Tap duration */
#define ADXL345_REG_DUR 0x21
/* Tap latency */
#define ADXL345_REG_LATENT 0x22
/* Tap window */
#define ADXL345_REG_WINDOW 0x23
/* Activity threshold */
#define ADXL345_REG_THRESH_ACT 0x24
/* Inactivity threshold */
#define ADXL345_REG_THRESH_INACT 0x25
/* Inactivity time */
#define ADXL345_REG_TIME_INACT 0x26
/* Axis enable control for activity and inactivity detection */
#define ADXL345_REG_ACT_INACT_CTRL 0x27
/* Free-fall threshold */
#define ADXL345_REG_THRESH_FF 0x28
/* Free-fall time */
#define ADXL345_REG_TIME_FF 0x29
/* Axis control for single tap or double tap */
#define ADXL345_REG_TAP_AXIS 0x2A
/* Source of single tap or double tap */
#define ADXL345_REG_ACT_TAP_STATUS 0x2B
/* Data rate and power mode control */
#define ADXL345_REG_BW_RATE 0x2C
#define ADXL345_REG_POWER_CTL 0x2D
#define ADXL345_REG_INT_ENABLE 0x2E
@ -34,19 +59,36 @@
#define ADXL345_INT_OVERRUN BIT(0)
#define ADXL345_INT_WATERMARK BIT(1)
#define ADXL345_INT_FREE_FALL BIT(2)
#define ADXL345_INT_INACTIVITY BIT(3)
#define ADXL345_INT_ACTIVITY BIT(4)
#define ADXL345_INT_DOUBLE_TAP BIT(5)
#define ADXL345_INT_SINGLE_TAP BIT(6)
#define ADXL345_INT_DATA_READY BIT(7)
/*
* BW_RATE bits - Bandwidth and output data rate. The default value is
* 0x0A, which translates to a 100 Hz output data rate
*/
#define ADXL345_BW_RATE GENMASK(3, 0)
#define ADXL345_BW_LOW_POWER BIT(4)
#define ADXL345_BASE_RATE_NANO_HZ 97656250LL
#define ADXL345_POWER_CTL_STANDBY 0x00
#define ADXL345_POWER_CTL_WAKEUP GENMASK(1, 0)
#define ADXL345_POWER_CTL_SLEEP BIT(2)
#define ADXL345_POWER_CTL_MEASURE BIT(3)
#define ADXL345_POWER_CTL_AUTO_SLEEP BIT(4)
#define ADXL345_POWER_CTL_LINK BIT(5)
#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) /* Set the g range */
#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) /* Left-justified (MSB) mode */
#define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */
#define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6) /* 3-wire SPI mode */
#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) /* Enable a self test */
/* Set the g range */
#define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0)
/* Data is left justified */
#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2)
/* Up to 13-bits resolution */
#define ADXL345_DATA_FORMAT_FULL_RES BIT(3)
#define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6)
#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7)
#define ADXL345_DATA_FORMAT_2G 0
#define ADXL345_DATA_FORMAT_4G 1
#define ADXL345_DATA_FORMAT_8G 2