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pwm: imx27: Use clk_bulk_*() API to simplify clock handling

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Simplify the clock handling logic by using the clk_bulk_*() API.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240910-pwm-v3-2-fbb047896618@nxp.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
This commit is contained in:
Frank Li 2024-09-10 15:07:19 -04:00 • committed by Uwe Kleine-König
parent a25351e4c7
commit f8e87e14b6
1 changed files with 22 additions and 41 deletions
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63
drivers/pwm/pwm-imx27.c
View file

@ -80,9 +80,12 @@
/* PWMPR register value of 0xffff has the same effect as 0xfffe */ /* PWMPR register value of 0xffff has the same effect as 0xfffe */
#define MX3_PWMPR_MAX 0xfffe #define MX3_PWMPR_MAX 0xfffe
static const char * const pwm_imx27_clks[] = {"ipg", "per"};
#define PWM_IMX27_PER 1
struct pwm_imx27_chip { struct pwm_imx27_chip {
struct clk *clk_ipg; struct clk_bulk_data clks[ARRAY_SIZE(pwm_imx27_clks)];
struct clk *clk_per; int clks_cnt;
void __iomem *mmio_base; void __iomem *mmio_base;
/* /*
@ -98,29 +101,6 @@ static inline struct pwm_imx27_chip *to_pwm_imx27_chip(struct pwm_chip *chip)
return pwmchip_get_drvdata(chip); return pwmchip_get_drvdata(chip);
} }
static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)
{
int ret;
ret = clk_prepare_enable(imx->clk_ipg);
if (ret)
return ret;
ret = clk_prepare_enable(imx->clk_per);
if (ret) {
clk_disable_unprepare(imx->clk_ipg);
return ret;
}
return 0;
}
static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)
{
clk_disable_unprepare(imx->clk_per);
clk_disable_unprepare(imx->clk_ipg);
}
static int pwm_imx27_get_state(struct pwm_chip *chip, static int pwm_imx27_get_state(struct pwm_chip *chip,
struct pwm_device *pwm, struct pwm_state *state) struct pwm_device *pwm, struct pwm_state *state)
{ {
@ -129,7 +109,7 @@ static int pwm_imx27_get_state(struct pwm_chip *chip,
u64 tmp; u64 tmp;
int ret; int ret;
ret = pwm_imx27_clk_prepare_enable(imx); ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);
if (ret < 0) if (ret < 0)
return ret; return ret;
@ -152,7 +132,7 @@ static int pwm_imx27_get_state(struct pwm_chip *chip,
} }
prescaler = MX3_PWMCR_PRESCALER_GET(val); prescaler = MX3_PWMCR_PRESCALER_GET(val);
pwm_clk = clk_get_rate(imx->clk_per); pwm_clk = clk_get_rate(imx->clks[PWM_IMX27_PER].clk);
val = readl(imx->mmio_base + MX3_PWMPR); val = readl(imx->mmio_base + MX3_PWMPR);
period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val; period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val;
@ -172,7 +152,7 @@ static int pwm_imx27_get_state(struct pwm_chip *chip,
tmp = NSEC_PER_SEC * (u64)(val) * prescaler; tmp = NSEC_PER_SEC * (u64)(val) * prescaler;
state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk); state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk);
pwm_imx27_clk_disable_unprepare(imx); clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);
return 0; return 0;
} }
@ -229,7 +209,7 @@ static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
int ret; int ret;
u32 cr; u32 cr;
clkrate = clk_get_rate(imx->clk_per); clkrate = clk_get_rate(imx->clks[PWM_IMX27_PER].clk);
c = clkrate * state->period; c = clkrate * state->period;
do_div(c, NSEC_PER_SEC); do_div(c, NSEC_PER_SEC);
@ -259,7 +239,7 @@ static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
if (pwm->state.enabled) { if (pwm->state.enabled) {
pwm_imx27_wait_fifo_slot(chip, pwm); pwm_imx27_wait_fifo_slot(chip, pwm);
} else { } else {
ret = pwm_imx27_clk_prepare_enable(imx); ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);
if (ret) if (ret)
return ret; return ret;
@ -381,7 +361,7 @@ static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm,
writel(cr, imx->mmio_base + MX3_PWMCR); writel(cr, imx->mmio_base + MX3_PWMCR);
if (!state->enabled) if (!state->enabled)
pwm_imx27_clk_disable_unprepare(imx); clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);
return 0; return 0;
} }
@ -403,21 +383,22 @@ static int pwm_imx27_probe(struct platform_device *pdev)
struct pwm_imx27_chip *imx; struct pwm_imx27_chip *imx;
int ret; int ret;
u32 pwmcr; u32 pwmcr;
int i;
chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*imx)); chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*imx));
if (IS_ERR(chip)) if (IS_ERR(chip))
return PTR_ERR(chip); return PTR_ERR(chip);
imx = to_pwm_imx27_chip(chip); imx = to_pwm_imx27_chip(chip);
imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); imx->clks_cnt = ARRAY_SIZE(pwm_imx27_clks);
if (IS_ERR(imx->clk_ipg)) for (i = 0; i < imx->clks_cnt; ++i)
return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg), imx->clks[i].id = pwm_imx27_clks[i];
"getting ipg clock failed\n");
imx->clk_per = devm_clk_get(&pdev->dev, "per"); ret = devm_clk_bulk_get(&pdev->dev, imx->clks_cnt, imx->clks);
if (IS_ERR(imx->clk_per))
return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per), if (ret)
"failed to get peripheral clock\n"); return dev_err_probe(&pdev->dev, ret,
"getting clocks failed\n");
chip->ops = &pwm_imx27_ops; chip->ops = &pwm_imx27_ops;
@ -425,14 +406,14 @@ static int pwm_imx27_probe(struct platform_device *pdev)
if (IS_ERR(imx->mmio_base)) if (IS_ERR(imx->mmio_base))
return PTR_ERR(imx->mmio_base); return PTR_ERR(imx->mmio_base);
ret = pwm_imx27_clk_prepare_enable(imx); ret = clk_bulk_prepare_enable(imx->clks_cnt, imx->clks);
if (ret) if (ret)
return ret; return ret;
/* keep clks on if pwm is running */ /* keep clks on if pwm is running */
pwmcr = readl(imx->mmio_base + MX3_PWMCR); pwmcr = readl(imx->mmio_base + MX3_PWMCR);
if (!(pwmcr & MX3_PWMCR_EN)) if (!(pwmcr & MX3_PWMCR_EN))
pwm_imx27_clk_disable_unprepare(imx); clk_bulk_disable_unprepare(imx->clks_cnt, imx->clks);
return devm_pwmchip_add(&pdev->dev, chip); return devm_pwmchip_add(&pdev->dev, chip);
} }