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drm/vc4: hvs: Make sure our channel is reset
In order to clear our intermediate FIFOs that might end up with a stale pixel, let's make sure our FIFO channel is reset every time our channel is setup. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://patchwork.freedesktop.org/patch/msgid/b34c562b36177c758dd2e9d84bceb07689bfbe05.1599120059.git-series.maxime@cerno.tech
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@ -205,6 +205,10 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc,
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u32 dispbkgndx;
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u32 dispctrl;
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HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
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HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET);
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HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
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/* Turn on the scaler, which will wait for vstart to start
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* compositing.
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* When feeding the transposer, we should operate in oneshot
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