public-mirrors/linux
1
0
Fork 0
mirror of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2025-09-18 22:14:16 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

drm/nouveau/nvdec: switch to instanced constructor

Browse source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2020-12-04 16:01:06 +10:00
parent b15147bd71
commit f8aeb13303
8 changed files with 26 additions and 38 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View file

@ -61,7 +61,6 @@ struct nvkm_device {
} acpi;
struct nvkm_nvenc *nvenc[3];
struct nvkm_nvdec *nvdec[3];
struct nvkm_pm *pm;
struct nvkm_engine *sec;
struct nvkm_sec2 *sec2;
@ -109,7 +108,6 @@ struct nvkm_device_chip {
#undef NVKM_LAYOUT_ONCE
int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_nvenc **);
int (*nvdec[3])(struct nvkm_device *, int idx, struct nvkm_nvdec **);
int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **);
int (*sec )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*sec2 )(struct nvkm_device *, int idx, struct nvkm_sec2 **);

1
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View file

@ -39,4 +39,5 @@ NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSENC , struct nvkm_engine , msenc)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPDEC , struct nvkm_engine , mspdec)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPPP , struct nvkm_engine , msppp)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSVLD , struct nvkm_engine , msvld)
NVKM_LAYOUT_INST(NVKM_ENGINE_NVDEC , struct nvkm_nvdec , nvdec, 3)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp)

2
drivers/gpu/drm/nouveau/include/nvkm/engine/nvdec.h
View file

@ -11,5 +11,5 @@ struct nvkm_nvdec {
struct nvkm_falcon falcon;
};
int gm107_nvdec_new(struct nvkm_device *, int, struct nvkm_nvdec **);
int gm107_nvdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_nvdec **);
#endif

7
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View file

@ -36,9 +36,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
[NVKM_ENGINE_NVENC0 ] = "nvenc0",
[NVKM_ENGINE_NVENC1 ] = "nvenc1",
[NVKM_ENGINE_NVENC2 ] = "nvenc2",
[NVKM_ENGINE_NVDEC0 ] = "nvdec0",
[NVKM_ENGINE_NVDEC1 ] = "nvdec1",
[NVKM_ENGINE_NVDEC2 ] = "nvdec2",
[NVKM_ENGINE_PM ] = "pm",
[NVKM_ENGINE_SEC ] = "sec",
[NVKM_ENGINE_SEC2 ] = "sec2",
@ -194,10 +191,6 @@ nvkm_subdev_ctor_(const struct nvkm_subdev_func *func, bool old,
subdev->type = NVKM_ENGINE_NVENC;
subdev->inst = subdev->index - NVKM_ENGINE_NVENC0;
break;
case NVKM_ENGINE_NVDEC0 ... NVKM_ENGINE_NVDEC_LAST:
subdev->type = NVKM_ENGINE_NVDEC;
subdev->inst = subdev->index - NVKM_ENGINE_NVDEC0;
break;
default:
break;
}

40
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View file

@ -1968,7 +1968,7 @@ nv117_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm107_fifo_new },
.gr = { 0x00000001, gm107_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.sw = gf100_sw_new,
};
@ -2036,7 +2036,7 @@ nv120_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm200_fifo_new },
.gr = { 0x00000001, gm200_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
.sw = gf100_sw_new,
@ -2072,7 +2072,7 @@ nv124_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm200_fifo_new },
.gr = { 0x00000001, gm200_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
.sw = gf100_sw_new,
@ -2108,7 +2108,7 @@ nv126_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm200_fifo_new },
.gr = { 0x00000001, gm200_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.sw = gf100_sw_new,
};
@ -2166,7 +2166,7 @@ nv130_chipset = {
.disp = { 0x00000001, gp100_disp_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = { 0x00000001, gp100_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
.nvenc[2] = gm107_nvenc_new,
@ -2201,7 +2201,7 @@ nv132_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = { 0x00000001, gp102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
.sec2 = gp102_sec2_new,
@ -2236,7 +2236,7 @@ nv134_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = { 0x00000001, gp104_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
.sec2 = gp102_sec2_new,
@ -2271,7 +2271,7 @@ nv136_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = { 0x00000001, gp104_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.sec2 = gp102_sec2_new,
.sw = gf100_sw_new,
@ -2305,7 +2305,7 @@ nv137_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = { 0x00000001, gp107_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
.sec2 = gp102_sec2_new,
@ -2340,7 +2340,7 @@ nv138_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = { 0x00000001, gp108_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.sec2 = gp108_sec2_new,
.sw = gf100_sw_new,
};
@ -2398,7 +2398,7 @@ nv140_chipset = {
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, gv100_fifo_new },
.gr = { 0x00000001, gv100_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
.nvenc[2] = gm107_nvenc_new,
@ -2434,7 +2434,7 @@ nv162_chipset = {
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, tu102_fifo_new },
.gr = { 0x00000001, tu102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.sec2 = tu102_sec2_new,
};
@ -2468,8 +2468,7 @@ nv164_chipset = {
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, tu102_fifo_new },
.gr = { 0x00000001, tu102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec[1] = gm107_nvdec_new,
.nvdec = { 0x00000003, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.sec2 = tu102_sec2_new,
};
@ -2503,9 +2502,7 @@ nv166_chipset = {
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, tu102_fifo_new },
.gr = { 0x00000001, tu102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec[1] = gm107_nvdec_new,
.nvdec[2] = gm107_nvdec_new,
.nvdec = { 0x00000007, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.sec2 = tu102_sec2_new,
};
@ -2539,7 +2536,7 @@ nv167_chipset = {
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, tu102_fifo_new },
.gr = { 0x00000001, tu102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.sec2 = tu102_sec2_new,
};
@ -2573,7 +2570,7 @@ nv168_chipset = {
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, tu102_fifo_new },
.gr = { 0x00000001, tu102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc[0] = gm107_nvenc_new,
.sec2 = tu102_sec2_new,
};
@ -3177,9 +3174,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
_(NVKM_ENGINE_NVENC0 , nvenc[0]);
_(NVKM_ENGINE_NVENC1 , nvenc[1]);
_(NVKM_ENGINE_NVENC2 , nvenc[2]);
_(NVKM_ENGINE_NVDEC0 , nvdec[0]);
_(NVKM_ENGINE_NVDEC1 , nvdec[1]);
_(NVKM_ENGINE_NVDEC2 , nvdec[2]);
_(NVKM_ENGINE_PM , pm);
_(NVKM_ENGINE_SEC , sec);
_(NVKM_ENGINE_SEC2 , sec2);
@ -3193,6 +3187,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
case NVKM_ENGINE_CE6:
case NVKM_ENGINE_CE7:
case NVKM_ENGINE_CE8:
case NVKM_ENGINE_NVDEC1:
case NVKM_ENGINE_NVDEC2:
break;
default:
WARN_ON(1);

4
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.c
View file

@ -37,7 +37,7 @@ nvkm_nvdec = {
int
nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *device,
int index, struct nvkm_nvdec **pnvdec)
enum nvkm_subdev_type type, int inst, struct nvkm_nvdec **pnvdec)
{
struct nvkm_nvdec *nvdec;
int ret;
@ -45,7 +45,7 @@ nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *device,
if (!(nvdec = *pnvdec = kzalloc(sizeof(*nvdec), GFP_KERNEL)))
return -ENOMEM;
ret = nvkm_engine_ctor(&nvkm_nvdec, device, index, true,
ret = nvkm_engine_ctor(&nvkm_nvdec, device, type, inst, true,
&nvdec->engine);
if (ret)
return ret;

4
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.c
View file

@ -56,8 +56,8 @@ gm107_nvdec_fwif[] = {
};
int
gm107_nvdec_new(struct nvkm_device *device, int index,
gm107_nvdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_nvdec **pnvdec)
{
return nvkm_nvdec_new_(gm107_nvdec_fwif, device, index, pnvdec);
return nvkm_nvdec_new_(gm107_nvdec_fwif, device, type, inst, pnvdec);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/nvdec/priv.h
View file

@ -14,6 +14,6 @@ struct nvkm_nvdec_fwif {
const struct nvkm_nvdec_func *func;
};
int nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif,
struct nvkm_device *, int, struct nvkm_nvdec **);
int nvkm_nvdec_new_(const struct nvkm_nvdec_fwif *fwif, struct nvkm_device *,
enum nvkm_subdev_type, int, struct nvkm_nvdec **);
#endif