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drm/amdgpu/gfx9: switch to amdgpu_gfx_rlc_init_microcode
switch to common helper to initialize rlc firmware for gfx9 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
5b41521268
commit
f6f8bb5989
1 changed files with 3 additions and 103 deletions
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@ -1091,27 +1091,6 @@ static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
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kfree(adev->gfx.rlc.register_list_format);
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}
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static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
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{
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const struct rlc_firmware_header_v2_1 *rlc_hdr;
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rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
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adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
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adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
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adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
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adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
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adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
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adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
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adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
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adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
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adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
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adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
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adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
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adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
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adev->gfx.rlc.reg_list_format_direct_reg_list_length =
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le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
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}
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static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
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{
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adev->gfx.me_fw_write_wait = false;
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@ -1353,11 +1332,7 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
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{
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char fw_name[30];
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int err;
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struct amdgpu_firmware_info *info = NULL;
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const struct common_firmware_header *header = NULL;
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const struct rlc_firmware_header_v2_0 *rlc_hdr;
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unsigned int *tmp = NULL;
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unsigned int i = 0;
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uint16_t version_major;
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uint16_t version_minor;
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uint32_t smu_version;
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@ -1386,88 +1361,13 @@ static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
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if (err)
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goto out;
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err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
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if (err)
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goto out;
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rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
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version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
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version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
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if (version_major == 2 && version_minor == 1)
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adev->gfx.rlc.is_rlc_v2_1 = true;
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adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
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adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
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adev->gfx.rlc.save_and_restore_offset =
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le32_to_cpu(rlc_hdr->save_and_restore_offset);
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adev->gfx.rlc.clear_state_descriptor_offset =
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le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
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adev->gfx.rlc.avail_scratch_ram_locations =
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le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
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adev->gfx.rlc.reg_restore_list_size =
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le32_to_cpu(rlc_hdr->reg_restore_list_size);
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adev->gfx.rlc.reg_list_format_start =
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le32_to_cpu(rlc_hdr->reg_list_format_start);
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adev->gfx.rlc.reg_list_format_separate_start =
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le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
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adev->gfx.rlc.starting_offsets_start =
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le32_to_cpu(rlc_hdr->starting_offsets_start);
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adev->gfx.rlc.reg_list_format_size_bytes =
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le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
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adev->gfx.rlc.reg_list_size_bytes =
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le32_to_cpu(rlc_hdr->reg_list_size_bytes);
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adev->gfx.rlc.register_list_format =
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kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
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adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
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if (!adev->gfx.rlc.register_list_format) {
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err = -ENOMEM;
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goto out;
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}
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tmp = (unsigned int *)((uintptr_t)rlc_hdr +
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le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
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for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
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adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
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adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
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tmp = (unsigned int *)((uintptr_t)rlc_hdr +
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le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
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for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
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adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
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if (adev->gfx.rlc.is_rlc_v2_1)
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gfx_v9_0_init_rlc_ext_microcode(adev);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
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info->fw = adev->gfx.rlc_fw;
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header = (const struct common_firmware_header *)info->fw->data;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
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if (adev->gfx.rlc.is_rlc_v2_1 &&
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adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
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adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
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adev->gfx.rlc.save_restore_list_srm_size_bytes) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
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info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
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info->fw = adev->gfx.rlc_fw;
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adev->firmware.fw_size +=
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ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
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}
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}
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err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
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out:
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if (err) {
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dev_err(adev->dev,
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