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drm/amd/amdgpu: support MES command SET_HW_RESOURCE1 in sriov
support MES command SET_HW_RESOURCE1 in sriov Signed-off-by: chongli2 <chongli2@amd.com> Reviewed-by: Jingwen Chen <Jingwen.Chen2@amd.com> Acked-by: Jingwen Chen <Jingwen.Chen2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
9ecef5b2d0
commit
f6ac084236
6 changed files with 85 additions and 3 deletions
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@ -141,6 +141,12 @@ struct amdgpu_mes {
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/* ip specific functions */
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const struct amdgpu_mes_funcs *funcs;
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/* mes resource_1 bo*/
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struct amdgpu_bo *resource_1;
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uint64_t resource_1_gpu_addr;
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void *resource_1_addr;
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};
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struct amdgpu_mes_process {
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@ -576,6 +576,11 @@ static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev)
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vf2pf_info->decode_usage = 0;
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vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr;
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vf2pf_info->mes_info_addr = (uint64_t)adev->mes.resource_1_gpu_addr;
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if (adev->mes.resource_1) {
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vf2pf_info->mes_info_size = adev->mes.resource_1->tbo.base.size;
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}
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vf2pf_info->checksum =
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amd_sriov_msg_checksum(
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vf2pf_info, vf2pf_info->header.size, 0, 0);
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@ -132,6 +132,8 @@ enum AMDGIM_FEATURE_FLAG {
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AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
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/* VCN RB decouple */
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AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7),
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/* MES info */
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AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8),
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};
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enum AMDGIM_REG_ACCESS_FLAG {
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@ -335,6 +337,8 @@ static inline bool is_virtual_machine(void)
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((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
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#define amdgpu_sriov_is_vcn_rb_decouple(adev) \
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((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE)
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#define amdgpu_sriov_is_mes_info_enable(adev) \
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((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE)
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bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
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void amdgpu_virt_init_setting(struct amdgpu_device *adev);
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int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
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@ -94,7 +94,8 @@ union amd_sriov_msg_feature_flags {
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uint32_t reg_indirect_acc : 1;
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uint32_t av1_support : 1;
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uint32_t vcn_rb_decouple : 1;
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uint32_t reserved : 24;
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uint32_t mes_info_enable : 1;
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uint32_t reserved : 23;
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} flags;
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uint32_t all;
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};
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@ -221,7 +222,7 @@ struct amd_sriov_msg_vf2pf_info_header {
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uint32_t reserved[2];
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};
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#define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (70)
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#define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (73)
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struct amd_sriov_msg_vf2pf_info {
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/* header contains size and version */
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struct amd_sriov_msg_vf2pf_info_header header;
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@ -265,7 +266,9 @@ struct amd_sriov_msg_vf2pf_info {
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uint32_t version;
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} ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
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uint64_t dummy_page_addr;
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/* FB allocated for guest MES to record UQ info */
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uint64_t mes_info_addr;
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uint32_t mes_info_size;
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/* reserved */
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uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];
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};
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@ -422,6 +422,36 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
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offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
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}
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static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes)
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{
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int size = 128 * PAGE_SIZE;
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int ret = 0;
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struct amdgpu_device *adev = mes->adev;
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union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_pkt;
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memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
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mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
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mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
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mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
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mes_set_hw_res_pkt.enable_mes_info_ctx = 1;
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ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&mes->resource_1,
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&mes->resource_1_gpu_addr,
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&mes->resource_1_addr);
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if (ret) {
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dev_err(adev->dev, "(%d) failed to create mes resource_1 bo\n", ret);
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return ret;
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}
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mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr;
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mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size;
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return mes_v11_0_submit_pkt_and_poll_completion(mes,
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&mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
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offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
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}
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static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
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.add_hw_queue = mes_v11_0_add_hw_queue,
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.remove_hw_queue = mes_v11_0_remove_hw_queue,
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@ -1203,6 +1233,14 @@ static int mes_v11_0_hw_init(void *handle)
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if (r)
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goto failure;
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if (amdgpu_sriov_is_mes_info_enable(adev)) {
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r = mes_v11_0_set_hw_resources_1(&adev->mes);
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if (r) {
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DRM_ERROR("failed mes_v11_0_set_hw_resources_1, r=%d\n", r);
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goto failure;
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}
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}
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r = mes_v11_0_query_sched_status(&adev->mes);
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if (r) {
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DRM_ERROR("MES is busy\n");
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@ -1226,6 +1264,11 @@ failure:
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static int mes_v11_0_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (amdgpu_sriov_is_mes_info_enable(adev)) {
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amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr,
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&adev->mes.resource_1_addr);
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}
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return 0;
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}
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@ -61,6 +61,7 @@ enum MES_SCH_API_OPCODE {
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MES_SCH_API_MISC = 14,
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MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15,
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MES_SCH_API_AMD_LOG = 16,
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MES_SCH_API_SET_HW_RSRC_1 = 19,
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MES_SCH_API_MAX = 0xFF
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};
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@ -238,6 +239,26 @@ union MESAPI_SET_HW_RESOURCES {
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI_SET_HW_RESOURCES_1 {
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struct {
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union MES_API_HEADER header;
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struct MES_API_STATUS api_status;
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uint64_t timestamp;
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union {
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struct {
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uint32_t enable_mes_info_ctx : 1;
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uint32_t reserved : 31;
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};
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uint32_t uint32_all;
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};
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uint64_t mes_info_ctx_mc_addr;
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uint32_t mes_info_ctx_size;
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uint32_t mes_kiq_unmap_timeout; // unit is 100ms
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};
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uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
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};
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union MESAPI__ADD_QUEUE {
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struct {
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union MES_API_HEADER header;
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