mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
net: airoha: Enable multiple IRQ lines support in airoha_eth driver.
EN7581 ethernet SoC supports 4 programmable IRQ lines for Tx and Rx interrupts. Enable multiple IRQ lines support. Map Rx/Tx queues to the available IRQ lines using the default scheme used in the vendor SDK: - IRQ0: rx queues [0-4],[7-9],15 - IRQ1: rx queues [21-30] - IRQ2: rx queues 5 - IRQ3: rx queues 6 Tx queues interrupts are managed by IRQ0. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://patch.msgid.link/20250418-airoha-eth-multi-irq-v1-2-1ab0083ca3c1@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Lorenzo Bianconi
Jakub Kicinski
parent
9439db26d3
commit
f252493e18
3 changed files with 206 additions and 59 deletions
|
|
@ -735,7 +735,6 @@ free_frag:
|
|||
static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget)
|
||||
{
|
||||
struct airoha_queue *q = container_of(napi, struct airoha_queue, napi);
|
||||
struct airoha_irq_bank *irq_bank = &q->qdma->irq_banks[0];
|
||||
int cur, done = 0;
|
||||
|
||||
do {
|
||||
|
|
@ -743,9 +742,20 @@ static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget)
|
|||
done += cur;
|
||||
} while (cur && done < budget);
|
||||
|
||||
if (done < budget && napi_complete(napi))
|
||||
airoha_qdma_irq_enable(irq_bank, QDMA_INT_REG_IDX1,
|
||||
RX_DONE_INT_MASK);
|
||||
if (done < budget && napi_complete(napi)) {
|
||||
struct airoha_qdma *qdma = q->qdma;
|
||||
int i, qid = q - &qdma->q_rx[0];
|
||||
int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1
|
||||
: QDMA_INT_REG_IDX2;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
|
||||
if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i)))
|
||||
continue;
|
||||
|
||||
airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg,
|
||||
BIT(qid % RX_DONE_HIGH_OFFSET));
|
||||
}
|
||||
}
|
||||
|
||||
return done;
|
||||
}
|
||||
|
|
@ -1178,17 +1188,24 @@ static int airoha_qdma_hw_init(struct airoha_qdma *qdma)
|
|||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
|
||||
/* clear pending irqs */
|
||||
for (i = 0; i < ARRAY_SIZE(qdma->irq_banks[0].irqmask); i++)
|
||||
airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff);
|
||||
|
||||
/* setup irqs */
|
||||
/* setup rx irqs */
|
||||
airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0,
|
||||
INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i)));
|
||||
airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1,
|
||||
INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i)));
|
||||
airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2,
|
||||
INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i)));
|
||||
airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3,
|
||||
INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i)));
|
||||
}
|
||||
/* setup tx irqs */
|
||||
airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0,
|
||||
INT_IDX0_MASK);
|
||||
airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX1,
|
||||
INT_IDX1_MASK);
|
||||
TX_COHERENT_LOW_INT_MASK | INT_TX_MASK);
|
||||
airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4,
|
||||
INT_IDX4_MASK);
|
||||
TX_COHERENT_HIGH_INT_MASK);
|
||||
|
||||
/* setup irq binding */
|
||||
for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
|
||||
|
|
@ -1235,6 +1252,7 @@ static irqreturn_t airoha_irq_handler(int irq, void *dev_instance)
|
|||
{
|
||||
struct airoha_irq_bank *irq_bank = dev_instance;
|
||||
struct airoha_qdma *qdma = irq_bank->qdma;
|
||||
u32 rx_intr_mask = 0, rx_intr1, rx_intr2;
|
||||
u32 intr[ARRAY_SIZE(irq_bank->irqmask)];
|
||||
int i;
|
||||
|
||||
|
|
@ -1247,18 +1265,25 @@ static irqreturn_t airoha_irq_handler(int irq, void *dev_instance)
|
|||
if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state))
|
||||
return IRQ_NONE;
|
||||
|
||||
if (intr[1] & RX_DONE_INT_MASK) {
|
||||
airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1,
|
||||
RX_DONE_INT_MASK);
|
||||
rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK;
|
||||
if (rx_intr1) {
|
||||
airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1);
|
||||
rx_intr_mask |= rx_intr1;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
|
||||
rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK;
|
||||
if (rx_intr2) {
|
||||
airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2);
|
||||
rx_intr_mask |= (rx_intr2 << 16);
|
||||
}
|
||||
|
||||
for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) {
|
||||
if (!qdma->q_rx[i].ndesc)
|
||||
continue;
|
||||
|
||||
if (intr[1] & BIT(i))
|
||||
if (rx_intr_mask & BIT(i))
|
||||
napi_schedule(&qdma->q_rx[i].napi);
|
||||
}
|
||||
}
|
||||
|
||||
if (intr[0] & INT_TX_MASK) {
|
||||
for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
|
||||
#define AIROHA_MAX_NUM_GDM_PORTS 4
|
||||
#define AIROHA_MAX_NUM_QDMA 2
|
||||
#define AIROHA_MAX_NUM_IRQ_BANKS 1
|
||||
#define AIROHA_MAX_NUM_IRQ_BANKS 4
|
||||
#define AIROHA_MAX_DSA_PORTS 7
|
||||
#define AIROHA_MAX_NUM_RSTS 3
|
||||
#define AIROHA_MAX_NUM_XSI_RSTS 5
|
||||
|
|
@ -453,6 +453,17 @@ struct airoha_flow_table_entry {
|
|||
unsigned long cookie;
|
||||
};
|
||||
|
||||
/* RX queue to IRQ mapping: BIT(q) in IRQ(n) */
|
||||
#define RX_IRQ0_BANK_PIN_MASK 0x839f
|
||||
#define RX_IRQ1_BANK_PIN_MASK 0x7fe00000
|
||||
#define RX_IRQ2_BANK_PIN_MASK 0x20
|
||||
#define RX_IRQ3_BANK_PIN_MASK 0x40
|
||||
#define RX_IRQ_BANK_PIN_MASK(_n) \
|
||||
(((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \
|
||||
((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \
|
||||
((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \
|
||||
RX_IRQ0_BANK_PIN_MASK)
|
||||
|
||||
struct airoha_irq_bank {
|
||||
struct airoha_qdma *qdma;
|
||||
|
||||
|
|
|
|||
|
|
@ -463,6 +463,26 @@
|
|||
#define IRQ0_FULL_INT_MASK BIT(1)
|
||||
#define IRQ0_INT_MASK BIT(0)
|
||||
|
||||
#define RX_COHERENT_LOW_INT_MASK \
|
||||
(RX15_COHERENT_INT_MASK | RX14_COHERENT_INT_MASK | \
|
||||
RX13_COHERENT_INT_MASK | RX12_COHERENT_INT_MASK | \
|
||||
RX11_COHERENT_INT_MASK | RX10_COHERENT_INT_MASK | \
|
||||
RX9_COHERENT_INT_MASK | RX8_COHERENT_INT_MASK | \
|
||||
RX7_COHERENT_INT_MASK | RX6_COHERENT_INT_MASK | \
|
||||
RX5_COHERENT_INT_MASK | RX4_COHERENT_INT_MASK | \
|
||||
RX3_COHERENT_INT_MASK | RX2_COHERENT_INT_MASK | \
|
||||
RX1_COHERENT_INT_MASK | RX0_COHERENT_INT_MASK)
|
||||
|
||||
#define RX_COHERENT_LOW_OFFSET __ffs(RX_COHERENT_LOW_INT_MASK)
|
||||
#define INT_RX0_MASK(_n) \
|
||||
(((_n) << RX_COHERENT_LOW_OFFSET) & RX_COHERENT_LOW_INT_MASK)
|
||||
|
||||
#define TX_COHERENT_LOW_INT_MASK \
|
||||
(TX7_COHERENT_INT_MASK | TX6_COHERENT_INT_MASK | \
|
||||
TX5_COHERENT_INT_MASK | TX4_COHERENT_INT_MASK | \
|
||||
TX3_COHERENT_INT_MASK | TX2_COHERENT_INT_MASK | \
|
||||
TX1_COHERENT_INT_MASK | TX0_COHERENT_INT_MASK)
|
||||
|
||||
#define TX_DONE_INT_MASK(_n) \
|
||||
((_n) ? IRQ1_INT_MASK | IRQ1_FULL_INT_MASK \
|
||||
: IRQ0_INT_MASK | IRQ0_FULL_INT_MASK)
|
||||
|
|
@ -471,17 +491,6 @@
|
|||
(IRQ1_INT_MASK | IRQ1_FULL_INT_MASK | \
|
||||
IRQ0_INT_MASK | IRQ0_FULL_INT_MASK)
|
||||
|
||||
#define INT_IDX0_MASK \
|
||||
(TX0_COHERENT_INT_MASK | TX1_COHERENT_INT_MASK | \
|
||||
TX2_COHERENT_INT_MASK | TX3_COHERENT_INT_MASK | \
|
||||
TX4_COHERENT_INT_MASK | TX5_COHERENT_INT_MASK | \
|
||||
TX6_COHERENT_INT_MASK | TX7_COHERENT_INT_MASK | \
|
||||
RX0_COHERENT_INT_MASK | RX1_COHERENT_INT_MASK | \
|
||||
RX2_COHERENT_INT_MASK | RX3_COHERENT_INT_MASK | \
|
||||
RX4_COHERENT_INT_MASK | RX7_COHERENT_INT_MASK | \
|
||||
RX8_COHERENT_INT_MASK | RX9_COHERENT_INT_MASK | \
|
||||
RX15_COHERENT_INT_MASK | INT_TX_MASK)
|
||||
|
||||
/* QDMA_CSR_INT_ENABLE2 */
|
||||
#define RX15_NO_CPU_DSCP_INT_MASK BIT(31)
|
||||
#define RX14_NO_CPU_DSCP_INT_MASK BIT(30)
|
||||
|
|
@ -516,19 +525,121 @@
|
|||
#define RX1_DONE_INT_MASK BIT(1)
|
||||
#define RX0_DONE_INT_MASK BIT(0)
|
||||
|
||||
#define RX_DONE_INT_MASK \
|
||||
(RX0_DONE_INT_MASK | RX1_DONE_INT_MASK | \
|
||||
RX2_DONE_INT_MASK | RX3_DONE_INT_MASK | \
|
||||
RX4_DONE_INT_MASK | RX7_DONE_INT_MASK | \
|
||||
RX8_DONE_INT_MASK | RX9_DONE_INT_MASK | \
|
||||
RX15_DONE_INT_MASK)
|
||||
#define INT_IDX1_MASK \
|
||||
(RX_DONE_INT_MASK | \
|
||||
RX0_NO_CPU_DSCP_INT_MASK | RX1_NO_CPU_DSCP_INT_MASK | \
|
||||
RX2_NO_CPU_DSCP_INT_MASK | RX3_NO_CPU_DSCP_INT_MASK | \
|
||||
RX4_NO_CPU_DSCP_INT_MASK | RX7_NO_CPU_DSCP_INT_MASK | \
|
||||
RX8_NO_CPU_DSCP_INT_MASK | RX9_NO_CPU_DSCP_INT_MASK | \
|
||||
RX15_NO_CPU_DSCP_INT_MASK)
|
||||
#define RX_NO_CPU_DSCP_LOW_INT_MASK \
|
||||
(RX15_NO_CPU_DSCP_INT_MASK | RX14_NO_CPU_DSCP_INT_MASK | \
|
||||
RX13_NO_CPU_DSCP_INT_MASK | RX12_NO_CPU_DSCP_INT_MASK | \
|
||||
RX11_NO_CPU_DSCP_INT_MASK | RX10_NO_CPU_DSCP_INT_MASK | \
|
||||
RX9_NO_CPU_DSCP_INT_MASK | RX8_NO_CPU_DSCP_INT_MASK | \
|
||||
RX7_NO_CPU_DSCP_INT_MASK | RX6_NO_CPU_DSCP_INT_MASK | \
|
||||
RX5_NO_CPU_DSCP_INT_MASK | RX4_NO_CPU_DSCP_INT_MASK | \
|
||||
RX3_NO_CPU_DSCP_INT_MASK | RX2_NO_CPU_DSCP_INT_MASK | \
|
||||
RX1_NO_CPU_DSCP_INT_MASK | RX0_NO_CPU_DSCP_INT_MASK)
|
||||
|
||||
#define RX_DONE_LOW_INT_MASK \
|
||||
(RX15_DONE_INT_MASK | RX14_DONE_INT_MASK | \
|
||||
RX13_DONE_INT_MASK | RX12_DONE_INT_MASK | \
|
||||
RX11_DONE_INT_MASK | RX10_DONE_INT_MASK | \
|
||||
RX9_DONE_INT_MASK | RX8_DONE_INT_MASK | \
|
||||
RX7_DONE_INT_MASK | RX6_DONE_INT_MASK | \
|
||||
RX5_DONE_INT_MASK | RX4_DONE_INT_MASK | \
|
||||
RX3_DONE_INT_MASK | RX2_DONE_INT_MASK | \
|
||||
RX1_DONE_INT_MASK | RX0_DONE_INT_MASK)
|
||||
|
||||
#define RX_NO_CPU_DSCP_LOW_OFFSET __ffs(RX_NO_CPU_DSCP_LOW_INT_MASK)
|
||||
#define INT_RX1_MASK(_n) \
|
||||
((((_n) << RX_NO_CPU_DSCP_LOW_OFFSET) & RX_NO_CPU_DSCP_LOW_INT_MASK) | \
|
||||
(RX_DONE_LOW_INT_MASK & (_n)))
|
||||
|
||||
/* QDMA_CSR_INT_ENABLE3 */
|
||||
#define RX31_NO_CPU_DSCP_INT_MASK BIT(31)
|
||||
#define RX30_NO_CPU_DSCP_INT_MASK BIT(30)
|
||||
#define RX29_NO_CPU_DSCP_INT_MASK BIT(29)
|
||||
#define RX28_NO_CPU_DSCP_INT_MASK BIT(28)
|
||||
#define RX27_NO_CPU_DSCP_INT_MASK BIT(27)
|
||||
#define RX26_NO_CPU_DSCP_INT_MASK BIT(26)
|
||||
#define RX25_NO_CPU_DSCP_INT_MASK BIT(25)
|
||||
#define RX24_NO_CPU_DSCP_INT_MASK BIT(24)
|
||||
#define RX23_NO_CPU_DSCP_INT_MASK BIT(23)
|
||||
#define RX22_NO_CPU_DSCP_INT_MASK BIT(22)
|
||||
#define RX21_NO_CPU_DSCP_INT_MASK BIT(21)
|
||||
#define RX20_NO_CPU_DSCP_INT_MASK BIT(20)
|
||||
#define RX19_NO_CPU_DSCP_INT_MASK BIT(19)
|
||||
#define RX18_NO_CPU_DSCP_INT_MASK BIT(18)
|
||||
#define RX17_NO_CPU_DSCP_INT_MASK BIT(17)
|
||||
#define RX16_NO_CPU_DSCP_INT_MASK BIT(16)
|
||||
#define RX31_DONE_INT_MASK BIT(15)
|
||||
#define RX30_DONE_INT_MASK BIT(14)
|
||||
#define RX29_DONE_INT_MASK BIT(13)
|
||||
#define RX28_DONE_INT_MASK BIT(12)
|
||||
#define RX27_DONE_INT_MASK BIT(11)
|
||||
#define RX26_DONE_INT_MASK BIT(10)
|
||||
#define RX25_DONE_INT_MASK BIT(9)
|
||||
#define RX24_DONE_INT_MASK BIT(8)
|
||||
#define RX23_DONE_INT_MASK BIT(7)
|
||||
#define RX22_DONE_INT_MASK BIT(6)
|
||||
#define RX21_DONE_INT_MASK BIT(5)
|
||||
#define RX20_DONE_INT_MASK BIT(4)
|
||||
#define RX19_DONE_INT_MASK BIT(3)
|
||||
#define RX18_DONE_INT_MASK BIT(2)
|
||||
#define RX17_DONE_INT_MASK BIT(1)
|
||||
#define RX16_DONE_INT_MASK BIT(0)
|
||||
|
||||
#define RX_NO_CPU_DSCP_HIGH_INT_MASK \
|
||||
(RX31_NO_CPU_DSCP_INT_MASK | RX30_NO_CPU_DSCP_INT_MASK | \
|
||||
RX29_NO_CPU_DSCP_INT_MASK | RX28_NO_CPU_DSCP_INT_MASK | \
|
||||
RX27_NO_CPU_DSCP_INT_MASK | RX26_NO_CPU_DSCP_INT_MASK | \
|
||||
RX25_NO_CPU_DSCP_INT_MASK | RX24_NO_CPU_DSCP_INT_MASK | \
|
||||
RX23_NO_CPU_DSCP_INT_MASK | RX22_NO_CPU_DSCP_INT_MASK | \
|
||||
RX21_NO_CPU_DSCP_INT_MASK | RX20_NO_CPU_DSCP_INT_MASK | \
|
||||
RX19_NO_CPU_DSCP_INT_MASK | RX18_NO_CPU_DSCP_INT_MASK | \
|
||||
RX17_NO_CPU_DSCP_INT_MASK | RX16_NO_CPU_DSCP_INT_MASK)
|
||||
|
||||
#define RX_DONE_HIGH_INT_MASK \
|
||||
(RX31_DONE_INT_MASK | RX30_DONE_INT_MASK | \
|
||||
RX29_DONE_INT_MASK | RX28_DONE_INT_MASK | \
|
||||
RX27_DONE_INT_MASK | RX26_DONE_INT_MASK | \
|
||||
RX25_DONE_INT_MASK | RX24_DONE_INT_MASK | \
|
||||
RX23_DONE_INT_MASK | RX22_DONE_INT_MASK | \
|
||||
RX21_DONE_INT_MASK | RX20_DONE_INT_MASK | \
|
||||
RX19_DONE_INT_MASK | RX18_DONE_INT_MASK | \
|
||||
RX17_DONE_INT_MASK | RX16_DONE_INT_MASK)
|
||||
|
||||
#define RX_DONE_INT_MASK (RX_DONE_HIGH_INT_MASK | RX_DONE_LOW_INT_MASK)
|
||||
#define RX_DONE_HIGH_OFFSET fls(RX_DONE_HIGH_INT_MASK)
|
||||
|
||||
#define INT_RX2_MASK(_n) \
|
||||
((RX_NO_CPU_DSCP_HIGH_INT_MASK & (_n)) | \
|
||||
(((_n) >> RX_DONE_HIGH_OFFSET) & RX_DONE_HIGH_INT_MASK))
|
||||
|
||||
/* QDMA_CSR_INT_ENABLE4 */
|
||||
#define RX31_COHERENT_INT_MASK BIT(31)
|
||||
#define RX30_COHERENT_INT_MASK BIT(30)
|
||||
#define RX29_COHERENT_INT_MASK BIT(29)
|
||||
#define RX28_COHERENT_INT_MASK BIT(28)
|
||||
#define RX27_COHERENT_INT_MASK BIT(27)
|
||||
#define RX26_COHERENT_INT_MASK BIT(26)
|
||||
#define RX25_COHERENT_INT_MASK BIT(25)
|
||||
#define RX24_COHERENT_INT_MASK BIT(24)
|
||||
#define RX23_COHERENT_INT_MASK BIT(23)
|
||||
#define RX22_COHERENT_INT_MASK BIT(22)
|
||||
#define RX21_COHERENT_INT_MASK BIT(21)
|
||||
#define RX20_COHERENT_INT_MASK BIT(20)
|
||||
#define RX19_COHERENT_INT_MASK BIT(19)
|
||||
#define RX18_COHERENT_INT_MASK BIT(18)
|
||||
#define RX17_COHERENT_INT_MASK BIT(17)
|
||||
#define RX16_COHERENT_INT_MASK BIT(16)
|
||||
|
||||
#define RX_COHERENT_HIGH_INT_MASK \
|
||||
(RX31_COHERENT_INT_MASK | RX30_COHERENT_INT_MASK | \
|
||||
RX29_COHERENT_INT_MASK | RX28_COHERENT_INT_MASK | \
|
||||
RX27_COHERENT_INT_MASK | RX26_COHERENT_INT_MASK | \
|
||||
RX25_COHERENT_INT_MASK | RX24_COHERENT_INT_MASK | \
|
||||
RX23_COHERENT_INT_MASK | RX22_COHERENT_INT_MASK | \
|
||||
RX21_COHERENT_INT_MASK | RX20_COHERENT_INT_MASK | \
|
||||
RX19_COHERENT_INT_MASK | RX18_COHERENT_INT_MASK | \
|
||||
RX17_COHERENT_INT_MASK | RX16_COHERENT_INT_MASK)
|
||||
|
||||
#define INT_RX3_MASK(_n) (RX_COHERENT_HIGH_INT_MASK & (_n))
|
||||
|
||||
/* QDMA_CSR_INT_ENABLE5 */
|
||||
#define TX31_COHERENT_INT_MASK BIT(31)
|
||||
|
|
@ -556,19 +667,19 @@
|
|||
#define TX9_COHERENT_INT_MASK BIT(9)
|
||||
#define TX8_COHERENT_INT_MASK BIT(8)
|
||||
|
||||
#define INT_IDX4_MASK \
|
||||
(TX8_COHERENT_INT_MASK | TX9_COHERENT_INT_MASK | \
|
||||
TX10_COHERENT_INT_MASK | TX11_COHERENT_INT_MASK | \
|
||||
TX12_COHERENT_INT_MASK | TX13_COHERENT_INT_MASK | \
|
||||
TX14_COHERENT_INT_MASK | TX15_COHERENT_INT_MASK | \
|
||||
TX16_COHERENT_INT_MASK | TX17_COHERENT_INT_MASK | \
|
||||
TX18_COHERENT_INT_MASK | TX19_COHERENT_INT_MASK | \
|
||||
TX20_COHERENT_INT_MASK | TX21_COHERENT_INT_MASK | \
|
||||
TX22_COHERENT_INT_MASK | TX23_COHERENT_INT_MASK | \
|
||||
TX24_COHERENT_INT_MASK | TX25_COHERENT_INT_MASK | \
|
||||
TX26_COHERENT_INT_MASK | TX27_COHERENT_INT_MASK | \
|
||||
TX28_COHERENT_INT_MASK | TX29_COHERENT_INT_MASK | \
|
||||
TX30_COHERENT_INT_MASK | TX31_COHERENT_INT_MASK)
|
||||
#define TX_COHERENT_HIGH_INT_MASK \
|
||||
(TX31_COHERENT_INT_MASK | TX30_COHERENT_INT_MASK | \
|
||||
TX29_COHERENT_INT_MASK | TX28_COHERENT_INT_MASK | \
|
||||
TX27_COHERENT_INT_MASK | TX26_COHERENT_INT_MASK | \
|
||||
TX25_COHERENT_INT_MASK | TX24_COHERENT_INT_MASK | \
|
||||
TX23_COHERENT_INT_MASK | TX22_COHERENT_INT_MASK | \
|
||||
TX21_COHERENT_INT_MASK | TX20_COHERENT_INT_MASK | \
|
||||
TX19_COHERENT_INT_MASK | TX18_COHERENT_INT_MASK | \
|
||||
TX17_COHERENT_INT_MASK | TX16_COHERENT_INT_MASK | \
|
||||
TX15_COHERENT_INT_MASK | TX14_COHERENT_INT_MASK | \
|
||||
TX13_COHERENT_INT_MASK | TX12_COHERENT_INT_MASK | \
|
||||
TX11_COHERENT_INT_MASK | TX10_COHERENT_INT_MASK | \
|
||||
TX9_COHERENT_INT_MASK | TX8_COHERENT_INT_MASK)
|
||||
|
||||
#define REG_TX_IRQ_BASE(_n) ((_n) ? 0x0048 : 0x0050)
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue