mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-09-18 22:14:16 +00:00
arm64: tegra: Fixup pinmux node names
Pinmux node names should have a pinmux- prefix and not use underscores. Fix up some cases that didn't follow those rules. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
parent
e9ddebc3a2
commit
efe499d885
5 changed files with 19 additions and 13 deletions
|
@ -62,7 +62,7 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinmux_default>;
|
||||
|
||||
pinmux_default: pinmux@0 {
|
||||
pinmux_default: pinmux {
|
||||
dap_mclk1_pw4 {
|
||||
nvidia,pins = "dap_mclk1_pw4";
|
||||
nvidia,function = "extperiph1";
|
||||
|
|
|
@ -632,7 +632,7 @@
|
|||
reg = <0x2430000 0x17000>;
|
||||
status = "okay";
|
||||
|
||||
pex_rst_c5_out_state: pex_rst_c5_out {
|
||||
pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
|
||||
pex_rst {
|
||||
nvidia,pins = "pex_l5_rst_n_pgg1";
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
|
@ -643,7 +643,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
|
||||
clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir {
|
||||
clkreq {
|
||||
nvidia,pins = "pex_l5_clkreq_n_pgg0";
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
|
|
|
@ -1293,14 +1293,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
dvfs_pwm_active_state: dvfs_pwm_active {
|
||||
dvfs_pwm_active_state: pinmux-dvfs-pwm-active {
|
||||
dvfs_pwm_pbb1 {
|
||||
nvidia,pins = "dvfs_pwm_pbb1";
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
|
||||
dvfs_pwm_inactive_state: dvfs_pwm_inactive {
|
||||
dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive {
|
||||
dvfs_pwm_pbb1 {
|
||||
nvidia,pins = "dvfs_pwm_pbb1";
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
|
|
|
@ -109,14 +109,14 @@
|
|||
};
|
||||
|
||||
pinmux@700008d4 {
|
||||
dvfs_pwm_active_state: dvfs_pwm_active {
|
||||
dvfs_pwm_active_state: pinmux-dvfs-pwm-active {
|
||||
dvfs_pwm_pbb1 {
|
||||
nvidia,pins = "dvfs_pwm_pbb1";
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
|
||||
dvfs_pwm_inactive_state: dvfs_pwm_inactive {
|
||||
dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive {
|
||||
dvfs_pwm_pbb1 {
|
||||
nvidia,pins = "dvfs_pwm_pbb1";
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
|
|
|
@ -554,42 +554,48 @@
|
|||
compatible = "nvidia,tegra210-pinmux";
|
||||
reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
|
||||
<0x0 0x70003000 0x0 0x294>; /* Mux registers */
|
||||
sdmmc1_3v3_drv: sdmmc1-3v3-drv {
|
||||
|
||||
sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv {
|
||||
sdmmc1 {
|
||||
nvidia,pins = "drive_sdmmc1";
|
||||
nvidia,pull-down-strength = <0x8>;
|
||||
nvidia,pull-up-strength = <0x8>;
|
||||
};
|
||||
};
|
||||
sdmmc1_1v8_drv: sdmmc1-1v8-drv {
|
||||
|
||||
sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv {
|
||||
sdmmc1 {
|
||||
nvidia,pins = "drive_sdmmc1";
|
||||
nvidia,pull-down-strength = <0x4>;
|
||||
nvidia,pull-up-strength = <0x3>;
|
||||
};
|
||||
};
|
||||
sdmmc2_1v8_drv: sdmmc2-1v8-drv {
|
||||
|
||||
sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv {
|
||||
sdmmc2 {
|
||||
nvidia,pins = "drive_sdmmc2";
|
||||
nvidia,pull-down-strength = <0x10>;
|
||||
nvidia,pull-up-strength = <0x10>;
|
||||
};
|
||||
};
|
||||
sdmmc3_3v3_drv: sdmmc3-3v3-drv {
|
||||
|
||||
sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv {
|
||||
sdmmc3 {
|
||||
nvidia,pins = "drive_sdmmc3";
|
||||
nvidia,pull-down-strength = <0x8>;
|
||||
nvidia,pull-up-strength = <0x8>;
|
||||
};
|
||||
};
|
||||
sdmmc3_1v8_drv: sdmmc3-1v8-drv {
|
||||
|
||||
sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv {
|
||||
sdmmc3 {
|
||||
nvidia,pins = "drive_sdmmc3";
|
||||
nvidia,pull-down-strength = <0x4>;
|
||||
nvidia,pull-up-strength = <0x3>;
|
||||
};
|
||||
};
|
||||
sdmmc4_1v8_drv: sdmmc4-1v8-drv {
|
||||
|
||||
sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv {
|
||||
sdmmc4 {
|
||||
nvidia,pins = "drive_sdmmc4";
|
||||
nvidia,pull-down-strength = <0x10>;
|
||||
|
|
Loading…
Add table
Reference in a new issue