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[media] mt9p031: Check return value of clk_prepare_enable/clk_set_rate

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clk_set_rate(), clk_prepare_enable() functions can fail, so check the return
values to avoid surprises.

Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Lad, Prabhakar 2014-01-21 02:20:57 -03:00 • committed by Mauro Carvalho Chehab
parent a970449e40
commit ee2d16d7b3
1 changed files with 12 additions and 3 deletions
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15
drivers/media/i2c/mt9p031.c
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@ -232,12 +232,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031)
struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
struct mt9p031_platform_data *pdata = mt9p031->pdata; struct mt9p031_platform_data *pdata = mt9p031->pdata;
int ret;
mt9p031->clk = devm_clk_get(&client->dev, NULL); mt9p031->clk = devm_clk_get(&client->dev, NULL);
if (IS_ERR(mt9p031->clk)) if (IS_ERR(mt9p031->clk))
return PTR_ERR(mt9p031->clk); return PTR_ERR(mt9p031->clk);
clk_set_rate(mt9p031->clk, pdata->ext_freq); ret = clk_set_rate(mt9p031->clk, pdata->ext_freq);
if (ret < 0)
return ret;
/* If the external clock frequency is out of bounds for the PLL use the /* If the external clock frequency is out of bounds for the PLL use the
* pixel clock divider only and disable the PLL. * pixel clock divider only and disable the PLL.
@ -318,8 +321,14 @@ static int mt9p031_power_on(struct mt9p031 *mt9p031)
return ret; return ret;
/* Enable clock */ /* Enable clock */
if (mt9p031->clk) if (mt9p031->clk) {
clk_prepare_enable(mt9p031->clk); ret = clk_prepare_enable(mt9p031->clk);
if (ret) {
regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators),
mt9p031->regulators);
return ret;
}
}
/* Now RESET_BAR must be high */ /* Now RESET_BAR must be high */
if (gpio_is_valid(mt9p031->reset)) { if (gpio_is_valid(mt9p031->reset)) {