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mfd: sec: Add support for S2MPU05 PMIC
Add support for Samsung's S2MPU05 PMIC. It's the primary PMIC used by Exynos7870 devices. It houses regulators (21 LDOs and 5 BUCKs) and a RTC clock device. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250301-exynos7870-pmic-regulators-v3-2-808d0b47a564@disroot.org Signed-off-by: Lee Jones <lee@kernel.org>
This commit is contained in:
Kaustabh Chakraborty
Lee Jones
parent
07ef6dc942
commit
ed33479b7b
5 changed files with 274 additions and 0 deletions
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@ -83,6 +83,11 @@ static const struct mfd_cell s2mpu02_devs[] = {
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{ .name = "s2mpu02-regulator", },
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};
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static const struct mfd_cell s2mpu05_devs[] = {
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{ .name = "s2mpu05-regulator", },
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{ .name = "s2mps15-rtc", },
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};
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static const struct of_device_id sec_dt_match[] = {
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{
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.compatible = "samsung,s5m8767-pmic",
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@ -108,6 +113,9 @@ static const struct of_device_id sec_dt_match[] = {
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}, {
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.compatible = "samsung,s2mpu02-pmic",
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.data = (void *)S2MPU02,
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}, {
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.compatible = "samsung,s2mpu05-pmic",
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.data = (void *)S2MPU05,
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}, {
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/* Sentinel */
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},
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@ -374,6 +382,10 @@ static int sec_pmic_probe(struct i2c_client *i2c)
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sec_devs = s2mpu02_devs;
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num_sec_devs = ARRAY_SIZE(s2mpu02_devs);
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break;
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case S2MPU05:
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sec_devs = s2mpu05_devs;
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num_sec_devs = ARRAY_SIZE(s2mpu05_devs);
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break;
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default:
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dev_err(&i2c->dev, "Unsupported device type (%lu)\n",
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sec_pmic->device_type);
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@ -14,6 +14,7 @@
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#include <linux/mfd/samsung/s2mps11.h>
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#include <linux/mfd/samsung/s2mps14.h>
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#include <linux/mfd/samsung/s2mpu02.h>
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#include <linux/mfd/samsung/s2mpu05.h>
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#include <linux/mfd/samsung/s5m8767.h>
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static const struct regmap_irq s2mps11_irqs[] = {
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@ -225,6 +226,26 @@ static const struct regmap_irq s2mpu02_irqs[] = {
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},
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};
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static const struct regmap_irq s2mpu05_irqs[] = {
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REGMAP_IRQ_REG(S2MPU05_IRQ_PWRONF, 0, S2MPU05_IRQ_PWRONF_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_PWRONR, 0, S2MPU05_IRQ_PWRONR_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_JIGONBF, 0, S2MPU05_IRQ_JIGONBF_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_JIGONBR, 0, S2MPU05_IRQ_JIGONBR_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_ACOKF, 0, S2MPU05_IRQ_ACOKF_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_ACOKR, 0, S2MPU05_IRQ_ACOKR_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_PWRON1S, 0, S2MPU05_IRQ_PWRON1S_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_MRB, 0, S2MPU05_IRQ_MRB_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_RTC60S, 1, S2MPU05_IRQ_RTC60S_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_RTCA1, 1, S2MPU05_IRQ_RTCA1_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_RTCA0, 1, S2MPU05_IRQ_RTCA0_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_SMPL, 1, S2MPU05_IRQ_SMPL_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_RTC1S, 1, S2MPU05_IRQ_RTC1S_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_WTSR, 1, S2MPU05_IRQ_WTSR_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_INT120C, 2, S2MPU05_IRQ_INT120C_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_INT140C, 2, S2MPU05_IRQ_INT140C_MASK),
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REGMAP_IRQ_REG(S2MPU05_IRQ_TSD, 2, S2MPU05_IRQ_TSD_MASK),
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};
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static const struct regmap_irq s5m8767_irqs[] = {
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[S5M8767_IRQ_PWRR] = {
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.reg_offset = 0,
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@ -339,6 +360,16 @@ static const struct regmap_irq_chip s2mpu02_irq_chip = {
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.ack_base = S2MPU02_REG_INT1,
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};
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static const struct regmap_irq_chip s2mpu05_irq_chip = {
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.name = "s2mpu05",
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.irqs = s2mpu05_irqs,
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.num_irqs = ARRAY_SIZE(s2mpu05_irqs),
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.num_regs = 3,
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.status_base = S2MPU05_REG_INT1,
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.mask_base = S2MPU05_REG_INT1M,
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.ack_base = S2MPU05_REG_INT1,
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};
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static const struct regmap_irq_chip s5m8767_irq_chip = {
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.name = "s5m8767",
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.irqs = s5m8767_irqs,
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@ -383,6 +414,9 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic)
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case S2MPU02:
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sec_irq_chip = &s2mpu02_irq_chip;
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break;
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case S2MPU05:
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sec_irq_chip = &s2mpu05_irq_chip;
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break;
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default:
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dev_err(sec_pmic->dev, "Unknown device type %lu\n",
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sec_pmic->device_type);
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@ -44,6 +44,7 @@ enum sec_device_type {
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S2MPS14X,
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S2MPS15X,
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S2MPU02,
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S2MPU05,
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};
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/**
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@ -150,6 +150,50 @@ enum s2mpu02_irq {
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/* Masks for interrupts are the same as in s2mps11 */
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#define S2MPS14_IRQ_TSD_MASK (1 << 2)
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enum s2mpu05_irq {
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S2MPU05_IRQ_PWRONF,
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S2MPU05_IRQ_PWRONR,
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S2MPU05_IRQ_JIGONBF,
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S2MPU05_IRQ_JIGONBR,
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S2MPU05_IRQ_ACOKF,
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S2MPU05_IRQ_ACOKR,
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S2MPU05_IRQ_PWRON1S,
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S2MPU05_IRQ_MRB,
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S2MPU05_IRQ_RTC60S,
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S2MPU05_IRQ_RTCA1,
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S2MPU05_IRQ_RTCA0,
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S2MPU05_IRQ_SMPL,
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S2MPU05_IRQ_RTC1S,
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S2MPU05_IRQ_WTSR,
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S2MPU05_IRQ_INT120C,
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S2MPU05_IRQ_INT140C,
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S2MPU05_IRQ_TSD,
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S2MPU05_IRQ_NR,
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};
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#define S2MPU05_IRQ_PWRONF_MASK BIT(0)
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#define S2MPU05_IRQ_PWRONR_MASK BIT(1)
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#define S2MPU05_IRQ_JIGONBF_MASK BIT(2)
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#define S2MPU05_IRQ_JIGONBR_MASK BIT(3)
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#define S2MPU05_IRQ_ACOKF_MASK BIT(4)
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#define S2MPU05_IRQ_ACOKR_MASK BIT(5)
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#define S2MPU05_IRQ_PWRON1S_MASK BIT(6)
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#define S2MPU05_IRQ_MRB_MASK BIT(7)
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#define S2MPU05_IRQ_RTC60S_MASK BIT(0)
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#define S2MPU05_IRQ_RTCA1_MASK BIT(1)
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#define S2MPU05_IRQ_RTCA0_MASK BIT(2)
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#define S2MPU05_IRQ_SMPL_MASK BIT(3)
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#define S2MPU05_IRQ_RTC1S_MASK BIT(4)
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#define S2MPU05_IRQ_WTSR_MASK BIT(5)
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#define S2MPU05_IRQ_INT120C_MASK BIT(0)
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#define S2MPU05_IRQ_INT140C_MASK BIT(1)
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#define S2MPU05_IRQ_TSD_MASK BIT(2)
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enum s5m8767_irq {
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S5M8767_IRQ_PWRR,
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S5M8767_IRQ_PWRF,
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183
include/linux/mfd/samsung/s2mpu05.h
Normal file
183
include/linux/mfd/samsung/s2mpu05.h
Normal file
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@ -0,0 +1,183 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd
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* Copyright (c) 2025 Kaustabh Chakraborty <kauschluss@disroot.org>
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*/
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#ifndef __LINUX_MFD_S2MPU05_H
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#define __LINUX_MFD_S2MPU05_H
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/* S2MPU05 registers */
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enum S2MPU05_reg {
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S2MPU05_REG_ID,
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S2MPU05_REG_INT1,
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S2MPU05_REG_INT2,
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S2MPU05_REG_INT3,
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S2MPU05_REG_INT1M,
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S2MPU05_REG_INT2M,
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S2MPU05_REG_INT3M,
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S2MPU05_REG_ST1,
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S2MPU05_REG_ST2,
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S2MPU05_REG_PWRONSRC,
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S2MPU05_REG_OFFSRC,
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S2MPU05_REG_BU_CHG,
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S2MPU05_REG_RTC_BUF,
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S2MPU05_REG_CTRL1,
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S2MPU05_REG_CTRL2,
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S2MPU05_REG_ETC_TEST,
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S2MPU05_REG_OTP_ADRL,
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S2MPU05_REG_OTP_ADRH,
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S2MPU05_REG_OTP_DATA,
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S2MPU05_REG_MON1SEL,
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S2MPU05_REG_MON2SEL,
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S2MPU05_REG_CTRL3,
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S2MPU05_REG_ETC_OTP,
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S2MPU05_REG_UVLO,
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S2MPU05_REG_TIME_CTRL1,
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S2MPU05_REG_TIME_CTRL2,
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S2MPU05_REG_B1CTRL1,
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S2MPU05_REG_B1CTRL2,
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S2MPU05_REG_B2CTRL1,
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S2MPU05_REG_B2CTRL2,
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S2MPU05_REG_B2CTRL3,
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S2MPU05_REG_B2CTRL4,
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S2MPU05_REG_B3CTRL1,
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S2MPU05_REG_B3CTRL2,
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S2MPU05_REG_B3CTRL3,
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S2MPU05_REG_B4CTRL1,
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S2MPU05_REG_B4CTRL2,
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S2MPU05_REG_B5CTRL1,
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S2MPU05_REG_B5CTRL2,
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S2MPU05_REG_BUCK_RAMP,
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S2MPU05_REG_LDO_DVS1,
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S2MPU05_REG_LDO_DVS9,
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S2MPU05_REG_LDO_DVS10,
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S2MPU05_REG_L1CTRL,
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S2MPU05_REG_L2CTRL,
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S2MPU05_REG_L3CTRL,
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S2MPU05_REG_L4CTRL,
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S2MPU05_REG_L5CTRL,
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S2MPU05_REG_L6CTRL,
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S2MPU05_REG_L7CTRL,
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S2MPU05_REG_L8CTRL,
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S2MPU05_REG_L9CTRL1,
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S2MPU05_REG_L9CTRL2,
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S2MPU05_REG_L10CTRL,
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S2MPU05_REG_L11CTRL1,
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S2MPU05_REG_L11CTRL2,
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S2MPU05_REG_L12CTRL,
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S2MPU05_REG_L13CTRL,
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S2MPU05_REG_L14CTRL,
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S2MPU05_REG_L15CTRL,
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S2MPU05_REG_L16CTRL,
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S2MPU05_REG_L17CTRL1,
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S2MPU05_REG_L17CTRL2,
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S2MPU05_REG_L18CTRL1,
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S2MPU05_REG_L18CTRL2,
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S2MPU05_REG_L19CTRL,
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S2MPU05_REG_L20CTRL,
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S2MPU05_REG_L21CTRL,
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S2MPU05_REG_L22CTRL,
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S2MPU05_REG_L23CTRL,
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S2MPU05_REG_L24CTRL,
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S2MPU05_REG_L25CTRL,
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S2MPU05_REG_L26CTRL,
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S2MPU05_REG_L27CTRL,
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S2MPU05_REG_L28CTRL,
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S2MPU05_REG_L29CTRL,
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S2MPU05_REG_L30CTRL,
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S2MPU05_REG_L31CTRL,
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S2MPU05_REG_L32CTRL,
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S2MPU05_REG_L33CTRL,
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S2MPU05_REG_L34CTRL,
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S2MPU05_REG_L35CTRL,
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S2MPU05_REG_LDO_DSCH1,
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S2MPU05_REG_LDO_DSCH2,
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S2MPU05_REG_LDO_DSCH3,
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S2MPU05_REG_LDO_DSCH4,
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S2MPU05_REG_LDO_DSCH5,
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S2MPU05_REG_LDO_CTRL1,
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S2MPU05_REG_LDO_CTRL2,
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S2MPU05_REG_TCXO_CTRL,
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S2MPU05_REG_SELMIF,
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};
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/* S2MPU05 regulator ids */
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enum S2MPU05_regulators {
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S2MPU05_LDO1,
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S2MPU05_LDO2,
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S2MPU05_LDO3,
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S2MPU05_LDO4,
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S2MPU05_LDO5,
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S2MPU05_LDO6,
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S2MPU05_LDO7,
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S2MPU05_LDO8,
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S2MPU05_LDO9,
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S2MPU05_LDO10,
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S2MPU05_LDO11,
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S2MPU05_LDO12,
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S2MPU05_LDO13,
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S2MPU05_LDO14,
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S2MPU05_LDO15,
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S2MPU05_LDO16,
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S2MPU05_LDO17,
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S2MPU05_LDO18,
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S2MPU05_LDO19,
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S2MPU05_LDO20,
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S2MPU05_LDO21,
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S2MPU05_LDO22,
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S2MPU05_LDO23,
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S2MPU05_LDO24,
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S2MPU05_LDO25,
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S2MPU05_LDO26,
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S2MPU05_LDO27,
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S2MPU05_LDO28,
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S2MPU05_LDO29,
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S2MPU05_LDO30,
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S2MPU05_LDO31,
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S2MPU05_LDO32,
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S2MPU05_LDO33,
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S2MPU05_LDO34,
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S2MPU05_LDO35,
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S2MPU05_BUCK1,
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S2MPU05_BUCK2,
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S2MPU05_BUCK3,
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S2MPU05_BUCK4,
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S2MPU05_BUCK5,
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S2MPU05_REGULATOR_MAX,
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};
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#define S2MPU05_SW_ENABLE_MASK 0x03
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#define S2MPU05_ENABLE_TIME_LDO 128
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#define S2MPU05_ENABLE_TIME_BUCK1 110
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#define S2MPU05_ENABLE_TIME_BUCK2 110
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#define S2MPU05_ENABLE_TIME_BUCK3 110
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#define S2MPU05_ENABLE_TIME_BUCK4 150
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#define S2MPU05_ENABLE_TIME_BUCK5 150
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#define S2MPU05_LDO_MIN1 800000
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#define S2MPU05_LDO_MIN2 1800000
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#define S2MPU05_LDO_MIN3 400000
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#define S2MPU05_LDO_STEP1 12500
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#define S2MPU05_LDO_STEP2 25000
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#define S2MPU05_BUCK_MIN1 400000
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#define S2MPU05_BUCK_MIN2 600000
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#define S2MPU05_BUCK_STEP1 6250
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#define S2MPU05_BUCK_STEP2 12500
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#define S2MPU05_RAMP_DELAY 12000 /* uV/uS */
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#define S2MPU05_ENABLE_SHIFT 6
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#define S2MPU05_ENABLE_MASK (0x03 << S2MPU05_ENABLE_SHIFT)
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#define S2MPU05_LDO_VSEL_MASK 0x3F
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#define S2MPU05_BUCK_VSEL_MASK 0xFF
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#define S2MPU05_LDO_N_VOLTAGES (S2MPU05_LDO_VSEL_MASK + 1)
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#define S2MPU05_BUCK_N_VOLTAGES (S2MPU05_BUCK_VSEL_MASK + 1)
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#define S2MPU05_PMIC_EN_SHIFT 6
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#endif /* __LINUX_MFD_S2MPU05_H */
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