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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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arm64: dts: mediatek: add display blocks support for the MT8365 SoC
- Add aliases for each display components to help display drivers. - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals for the LED driver of mobile LCM. - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane output) - Add the display mutex support. - Add the following display component support: - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20231023-display-support-v7-5-6703f3e26831@baylibre.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Alexandre Mergnat
AngeloGioacchino Del Regno
parent
be035e4a26
commit
ec207ea7f6
1 changed files with 336 additions and 0 deletions
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@ -10,6 +10,7 @@
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#include <dt-bindings/clock/mediatek,mt8365-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/memory/mediatek,mt8365-larb-port.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/mediatek,mt8365-power.h>
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@ -19,6 +20,19 @@
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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aal0 = &aal0;
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ccorr0 = &ccorr0;
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color0 = &color0;
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dither0 = &dither0;
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dpi0 = &dpi0;
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dsi0 = &dsi0;
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gamma0 = &gamma0;
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ovl0 = &ovl0;
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rdma0 = &rdma0;
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rdma1 = &rdma1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -609,6 +623,15 @@
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status = "disabled";
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};
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disp_pwm: pwm@1100e000 {
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compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm";
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reg = <0 0x1100e000 0 0x1000>;
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clock-names = "main", "mm";
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clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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#pwm-cells = <2>;
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};
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i2c3: i2c@1100f000 {
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compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
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reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
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@ -705,6 +728,15 @@
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status = "disabled";
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};
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mipi_tx0: dsi-phy@11c00000 {
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compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx";
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reg = <0 0x11c00000 0 0x800>;
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clock-output-names = "mipi_tx0_pll";
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clocks = <&clk26m>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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};
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u3phy: t-phy@11cc0000 {
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compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
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#address-cells = <1>;
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@ -732,6 +764,26 @@
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compatible = "mediatek,mt8365-mmsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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mmsys_main: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ovl0_in>;
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};
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mmsys_ext: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&rdma1_in>;
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};
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};
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};
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mutex: mutex@14001000 {
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compatible = "mediatek,mt8365-disp-mutex";
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reg = <0 0x14001000 0 0x1000>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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};
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smi_common: smi@14002000 {
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@ -757,6 +809,290 @@
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mediatek,larb-id = <0>;
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};
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ovl0: ovl@1400b000 {
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compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl";
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reg = <0 0x1400b000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MM_DISP_OVL0>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
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iommus = <&iommu M4U_PORT_DISP_OVL0>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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ovl0_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mmsys_main>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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ovl0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&rdma0_in>;
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};
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};
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};
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};
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rdma0: rdma@1400d000 {
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compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma";
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reg = <0 0x1400d000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>;
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interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
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iommus = <&iommu M4U_PORT_DISP_RDMA0>;
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mediatek,rdma-fifo-size = <5120>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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rdma0_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ovl0_out>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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rdma0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&color0_in>;
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};
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};
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};
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};
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color0: color@1400f000 {
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compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color";
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reg = <0 0x1400f000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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color0_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&rdma0_out>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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color0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ccorr0_in>;
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};
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};
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};
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};
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ccorr0: ccorr@14010000 {
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compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr";
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reg = <0 0x14010000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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ccorr0_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&color0_out>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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ccorr0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&aal0_in>;
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};
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};
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};
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};
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aal0: aal@14011000 {
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compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal";
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reg = <0 0x14011000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MM_DISP_AAL0>;
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interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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aal0_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ccorr0_out>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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aal0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&gamma0_in>;
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};
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};
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};
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};
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gamma0: gamma@14012000 {
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compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma";
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reg = <0 0x14012000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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gamma0_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&aal0_out>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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gamma0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dither0_in>;
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};
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};
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};
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};
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dither0: dither@14013000 {
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compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither";
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reg = <0 0x14013000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>;
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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dither0_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&gamma0_out>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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dither0_out: endpoint@0 {
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reg = <0>;
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};
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};
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};
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};
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dsi0: dsi@14014000 {
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compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi";
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reg = <0 0x14014000 0 0x1000>;
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clock-names = "engine", "digital", "hs";
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clocks = <&mmsys CLK_MM_MM_DSI0>,
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<&mmsys CLK_MM_DSI0_DIG_DSI>,
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<&mipi_tx0>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
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phy-names = "dphy";
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phys = <&mipi_tx0>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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};
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rdma1: rdma@14016000 {
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compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma";
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reg = <0 0x14016000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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iommus = <&iommu M4U_PORT_DISP_RDMA1>;
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mediatek,rdma-fifo-size = <2048>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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rdma1_in: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&mmsys_ext>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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rdma1_out: endpoint@1 {
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reg = <1>;
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};
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};
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};
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};
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dpi0: dpi@14018000 {
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compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi";
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reg = <0 0x14018000 0 0x1000>;
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clocks = <&mmsys CLK_MM_DPI0_DPI0>,
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<&mmsys CLK_MM_MM_DPI0>,
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<&apmixedsys CLK_APMIXED_LVDSPLL>;
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clock-names = "pixel", "engine", "pll";
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
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status = "disabled";
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};
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camsys: syscon@15000000 {
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compatible = "mediatek,mt8365-imgsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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