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Two new 32bit SoC were added, the rv1126 and rk3128.

Browse source 
New boards are thr rk3128-eval-board, and a number of rv1126-based compute
 modules from Edgeble AI.
 
 Also included are some dt-binding improvements with relevant Acks from
 maintainers when the changes touch these areas.
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Merge tag 'v6.3-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Two new 32bit SoC were added, the rv1126 and rk3128.

New boards are thr rk3128-eval-board, and a number of rv1126-based compute
modules from Edgeble AI.

Also included are some dt-binding improvements with relevant Acks from
maintainers when the changes touch these areas.

* tag 'v6.3-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  dt-bindings: phy: rename phy-rockchip-inno-usb2.yaml
  dt-bindings: soc: rockchip: grf: add rockchip,rk3288-dp-phy.yaml
  dt-bindings: phy: rockchip: convert rockchip-dp-phy.txt to yaml
  ARM: dts: rockchip: Enable Ethernet on rv1126 Neu2-IO
  ARM: dts: rockchip: Add Ethernet GMAC node for RV1126
  ARM: dts: rockchip: Add ethernet rgmiim1 pin-control for rv1126
  dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 6
  ARM: dts: rockchip: add brcmf node to rk3066a-mk808
  ARM: dts: rockchip: add space between label and nodename nfc pinctrl on rk3128
  ARM: dts: rockchip: add rk3128-evb
  ARM: dts: rockchip: add rk3128 soc dtsi
  dt-bindings: arm: rockchip: Add Rockchip RK3128 Evaluation board
  ARM: dts: rockchip: Add Edgeble Neural Compute Module 2(Neu2) IO board
  ARM: dts: rockchip: Add Edgeble RV1126 Neural Compute Module 2(Neu2)
  dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 2
  dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd.
  ARM: dts: rockchip: Add Rockchip RV1126 SoC
  ARM: dts: rockchip: Add Rockchip RV1126 pinctrl
  dt-bindings: arm: rockchip: Add pmu compatible for rv1126

Link: https://lore.kernel.org/r/5651506.31r3eYUQgx@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-02-03 14:11:08 +01:00
commit eacef7cc52
16 changed files with 2259 additions and 31 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
Documentation/devicetree/bindings/arm/rockchip.yaml
View file

@ -90,6 +90,18 @@ properties:
- const: chipspark,rayeager-px2
- const: rockchip,rk3066a
- description: Edgeble Neural Compute Module 2(Neu2) SoM based boards
items:
- const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board
- const: edgeble,neural-compute-module-2 # Edgeble Neural Compute Module 2 SoM
- const: rockchip,rv1126
- description: Edgeble Neural Compute Module 6(Neu6) Model A SoM based boards
items:
- const: edgeble,neural-compute-module-6a-io # Edgeble Neural Compute Module 6A IO Board
- const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM
- const: rockchip,rk3588
- description: Elgin RV1108 R1
items:
- const: elgin,rv1108-r1
@ -723,6 +735,11 @@ properties:
- const: rockchip,rk3036-evb
- const: rockchip,rk3036
- description: Rockchip RK3128 Evaluation board
items:
- const: rockchip,rk3128-evb
- const: rockchip,rk3128
- description: Rockchip RK3228 Evaluation board
items:
- const: rockchip,rk3228-evb

2
Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
View file

@ -27,6 +27,7 @@ select:
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- rockchip,rk3588-pmu
- rockchip,rv1126-pmu
required:
- compatible
@ -43,6 +44,7 @@ properties:
- rockchip,rk3399-pmu
- rockchip,rk3568-pmu
- rockchip,rk3588-pmu
- rockchip,rv1126-pmu
- const: syscon
- const: simple-mfd

2
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml → Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
View file

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
$id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip USB2.0 phy with inno IP block

41
Documentation/devicetree/bindings/phy/rockchip,rk3288-dp-phy.yaml Normal file
View file

@ -0,0 +1,41 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip specific extensions to the Analogix Display Port PHY
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
const: rockchip,rk3288-dp-phy
clocks:
maxItems: 1
clock-names:
const: 24m
"#phy-cells":
const: 0
required:
- compatible
- clocks
- clock-names
- "#phy-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3288-cru.h>
edp-phy {
compatible = "rockchip,rk3288-dp-phy";
clocks = <&cru SCLK_EDP_24M>;
clock-names = "24m";
#phy-cells = <0>;
};

26
Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
View file

@ -1,26 +0,0 @@
Rockchip specific extensions to the Analogix Display Port PHY
------------------------------------
Required properties:
- compatible : should be one of the following supported values:
- "rockchip.rk3288-dp-phy"
- clocks: from common clock binding: handle to dp clock.
of memory mapped region.
- clock-names: from common clock binding:
Required elements: "24m"
- #phy-cells : from the generic PHY bindings, must be 0;
Example:
grf: syscon@ff770000 {
compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
...
edp_phy: edp-phy {
compatible = "rockchip,rk3288-dp-phy";
clocks = <&cru SCLK_EDP_24M>;
clock-names = "24m";
#phy-cells = <0>;
};
};

7
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
View file

@ -97,8 +97,9 @@ allOf:
then:
properties:
edp-phy:
description:
Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
type: object
$ref: /schemas/phy/rockchip,rk3288-dp-phy.yaml#
unevaluatedProperties: false
- if:
properties:
@ -205,7 +206,7 @@ allOf:
"usb2phy@[0-9a-f]+$":
type: object
$ref: "/schemas/phy/phy-rockchip-inno-usb2.yaml#"
$ref: /schemas/phy/rockchip,inno-usb2phy.yaml#
unevaluatedProperties: false

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View file

@ -378,6 +378,8 @@ patternProperties:
description: EBV Elektronik
"^eckelmann,.*":
description: Eckelmann AG
"^edgeble,.*":
description: Edgeble AI Technologies Pvt. Ltd.
"^edimax,.*":
description: EDIMAX Technology Co., Ltd
"^edt,.*":

2
MAINTAINERS
View file

@ -2807,7 +2807,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml
F: arch/arm/boot/dts/rk3*
F: arch/arm/boot/dts/rv1108*
F: arch/arm/boot/dts/rv11*
F: arch/arm/mach-rockchip/
F: drivers/*/*/*rockchip*
F: drivers/*/*rockchip*

2
arch/arm/boot/dts/Makefile
View file

@ -1132,12 +1132,14 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb \
rv1126-edgeble-neu2-io.dtb \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
rk3066a-marsboard.dtb \
rk3066a-mk808.dtb \
rk3066a-rayeager.dtb \
rk3128-evb.dtb \
rk3188-bqedison2qc.dtb \
rk3188-px3-evb.dtb \
rk3188-radxarock.dtb \

7
arch/arm/boot/dts/rk3066a-mk808.dts
View file

@ -157,7 +157,14 @@
pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
pinctrl-names = "default";
vmmc-supply = <&vcc_wifi>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};
&nfc {

109
arch/arm/boot/dts/rk3128-evb.dts Normal file
View file

@ -0,0 +1,109 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include "rk3128.dtsi"
/ {
model = "Rockchip RK3128 Evaluation board";
compatible = "rockchip,rk3128-evb", "rockchip,rk3128";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
i2c1 = &i2c1;
mmc0 = &emmc;
};
chosen {
stdout-path = &uart2;
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
vcc5v0_otg: vcc5v0-otg-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc5v0_otg";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc5v0_host";
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&emmc {
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&i2c1 {
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-output-names = "xin32k";
};
};
&usb2phy {
status = "okay";
};
&usb2phy_host {
status = "okay";
};
&usb2phy_otg {
status = "okay";
};
&usb_host_ehci {
status = "okay";
};
&usb_host_ohci {
status = "okay";
};
&usb_otg {
vbus-supply = <&vcc5v0_otg>;
status = "okay";
};
&pinctrl {
usb-host {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-otg {
otg_vbus_drv: otg-vbus-drv {
rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

916
arch/arm/boot/dts/rk3128.dtsi Normal file
View file

@ -0,0 +1,916 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2017 Rockchip Electronics Co., Ltd
*/
#include <dt-bindings/clock/rk3128-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
/ {
compatible = "rockchip,rk3128";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
operating-points = <
/* KHz uV */
816000 1000000
>;
#cooling-cells = <2>; /* min followed by max */
};
cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
};
cpu2: cpu@f02 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf02>;
};
cpu3: cpu@f03 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf03>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
arm,cpu-registers-not-fw-configured;
clock-frequency = <24000000>;
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
pmu: syscon@100a0000 {
compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
reg = <0x100a0000 0x1000>;
};
gic: interrupt-controller@10139000 {
compatible = "arm,cortex-a7-gic";
reg = <0x10139000 0x1000>,
<0x1013a000 0x1000>,
<0x1013c000 0x2000>,
<0x1013e000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
};
usb_otg: usb@10180000 {
compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
reg = <0x10180000 0x40000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
dr_mode = "otg";
phys = <&usb2phy_otg>;
phy-names = "usb2-phy";
status = "disabled";
};
usb_host_ehci: usb@101c0000 {
compatible = "generic-ehci";
reg = <0x101c0000 0x20000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2phy_host>;
phy-names = "usb";
status = "disabled";
};
usb_host_ohci: usb@101e0000 {
compatible = "generic-ohci";
reg = <0x101e0000 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2phy_host>;
phy-names = "usb";
status = "disabled";
};
sdmmc: mmc@10214000 {
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
dmas = <&pdma 10>;
dma-names = "rx-tx";
fifo-depth = <256>;
max-frequency = <150000000>;
resets = <&cru SRST_SDMMC>;
reset-names = "reset";
status = "disabled";
};
sdio: mmc@10218000 {
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10218000 0x4000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
dmas = <&pdma 11>;
dma-names = "rx-tx";
fifo-depth = <256>;
max-frequency = <150000000>;
resets = <&cru SRST_SDIO>;
reset-names = "reset";
status = "disabled";
};
emmc: mmc@1021c000 {
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x1021c000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
dmas = <&pdma 12>;
dma-names = "rx-tx";
fifo-depth = <256>;
max-frequency = <150000000>;
resets = <&cru SRST_EMMC>;
reset-names = "reset";
status = "disabled";
};
nfc: nand-controller@10500000 {
compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
reg = <0x10500000 0x4000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
clock-names = "ahb", "nfc";
pinctrl-names = "default";
pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
&flash_dqs &flash_rdn &flash_rdy &flash_wrn>;
status = "disabled";
};
cru: clock-controller@20000000 {
compatible = "rockchip,rk3128-cru";
reg = <0x20000000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>;
assigned-clock-rates = <594000000>;
};
grf: syscon@20008000 {
compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
reg = <0x20008000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
usb2phy: usb2phy@17c {
compatible = "rockchip,rk3128-usb2phy";
reg = <0x017c 0x0c>;
clocks = <&cru SCLK_OTGPHY0>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy";
#clock-cells = <0>;
status = "disabled";
usb2phy_host: host-port {
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "linestate";
#phy-cells = <0>;
status = "disabled";
};
usb2phy_otg: otg-port {
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
#phy-cells = <0>;
status = "disabled";
};
};
};
timer0: timer@20044000 {
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>;
clock-names = "pclk", "timer";
};
timer1: timer@20044020 {
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044020 0x20>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>;
clock-names = "pclk", "timer";
};
timer2: timer@20044040 {
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044040 0x20>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>;
clock-names = "pclk", "timer";
};
timer3: timer@20044060 {
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044060 0x20>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>;
clock-names = "pclk", "timer";
};
timer4: timer@20044080 {
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x20044080 0x20>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>;
clock-names = "pclk", "timer";
};
timer5: timer@200440a0 {
compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
reg = <0x200440a0 0x20>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&xin24m>;
clock-names = "pclk", "timer";
};
watchdog: watchdog@2004c000 {
compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
reg = <0x2004c000 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_WDT>;
status = "disabled";
};
pwm0: pwm@20050000 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050000 0x10>;
clocks = <&cru PCLK_PWM>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
#pwm-cells = <3>;
status = "disabled";
};
pwm1: pwm@20050010 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050010 0x10>;
clocks = <&cru PCLK_PWM>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
#pwm-cells = <3>;
status = "disabled";
};
pwm2: pwm@20050020 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050020 0x10>;
clocks = <&cru PCLK_PWM>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
#pwm-cells = <3>;
status = "disabled";
};
pwm3: pwm@20050030 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050030 0x10>;
clocks = <&cru PCLK_PWM>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
#pwm-cells = <3>;
status = "disabled";
};
i2c1: i2c@20056000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <0x20056000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@2005a000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <0x2005a000 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@2005e000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <0x2005e000 0x1000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart0: serial@20060000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20060000 0x100>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
dmas = <&pdma 2>, <&pdma 3>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart1: serial@20064000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20064000 0x100>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
dmas = <&pdma 4>, <&pdma 5>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart2: serial@20068000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20068000 0x100>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
dmas = <&pdma 6>, <&pdma 7>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
saradc: saradc@2006c000 {
compatible = "rockchip,saradc";
reg = <0x2006c000 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;
reset-names = "saradc-apb";
#io-channel-cells = <1>;
status = "disabled";
};
i2c0: i2c@20072000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <20072000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@20074000 {
compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
reg = <0x20074000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
dmas = <&pdma 8>, <&pdma 9>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pdma: dma-controller@20078000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20078000 0x4000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
arm,pl330-broken-no-flushp;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
pinctrl: pinctrl {
compatible = "rockchip,rk3128-pinctrl";
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio@2007c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2007c000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@20088000 {
compatible = "rockchip,gpio-bank";
reg = <0x20088000 0x100>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pcfg_pull_default: pcfg-pull-default {
bias-pull-pin-default;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
};
emmc_cmd1: emmc-cmd1 {
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
};
emmc_pwr: emmc-pwr {
rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
};
emmc_bus1: emmc-bus1 {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
};
emmc_bus4: emmc-bus4 {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
<1 RK_PD1 2 &pcfg_pull_default>,
<1 RK_PD2 2 &pcfg_pull_default>,
<1 RK_PD3 2 &pcfg_pull_default>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
<1 RK_PD1 2 &pcfg_pull_default>,
<1 RK_PD2 2 &pcfg_pull_default>,
<1 RK_PD3 2 &pcfg_pull_default>,
<1 RK_PD4 2 &pcfg_pull_default>,
<1 RK_PD5 2 &pcfg_pull_default>,
<1 RK_PD6 2 &pcfg_pull_default>,
<1 RK_PD7 2 &pcfg_pull_default>;
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
<2 RK_PB1 3 &pcfg_pull_default>,
<2 RK_PB3 3 &pcfg_pull_default>,
<2 RK_PB4 3 &pcfg_pull_default>,
<2 RK_PB5 3 &pcfg_pull_default>,
<2 RK_PB6 3 &pcfg_pull_default>,
<2 RK_PC0 3 &pcfg_pull_default>,
<2 RK_PC1 3 &pcfg_pull_default>,
<2 RK_PC2 3 &pcfg_pull_default>,
<2 RK_PC3 3 &pcfg_pull_default>,
<2 RK_PD1 3 &pcfg_pull_default>,
<2 RK_PC4 4 &pcfg_pull_default>,
<2 RK_PC5 4 &pcfg_pull_default>,
<2 RK_PC6 4 &pcfg_pull_default>,
<2 RK_PC7 4 &pcfg_pull_default>;
};
rmii_pins: rmii-pins {
rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
<2 RK_PB4 3 &pcfg_pull_default>,
<2 RK_PB5 3 &pcfg_pull_default>,
<2 RK_PB6 3 &pcfg_pull_default>,
<2 RK_PB7 3 &pcfg_pull_default>,
<2 RK_PC0 3 &pcfg_pull_default>,
<2 RK_PC1 3 &pcfg_pull_default>,
<2 RK_PC2 3 &pcfg_pull_default>,
<2 RK_PC3 3 &pcfg_pull_default>,
<2 RK_PD1 3 &pcfg_pull_default>;
};
};
hdmi {
hdmii2c_xfer: hdmii2c-xfer {
rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
<0 RK_PA7 2 &pcfg_pull_none>;
};
hdmi_hpd: hdmi-hpd {
rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
};
hdmi_cec: hdmi-cec {
rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
<0 RK_PA1 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
<0 RK_PA3 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
<2 RK_PC5 3 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
<0 RK_PA7 1 &pcfg_pull_none>;
};
};
i2s {
i2s_bus: i2s-bus {
rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
<0 RK_PB1 1 &pcfg_pull_none>,
<0 RK_PB3 1 &pcfg_pull_none>,
<0 RK_PB4 1 &pcfg_pull_none>,
<0 RK_PB5 1 &pcfg_pull_none>,
<0 RK_PB6 1 &pcfg_pull_none>;
};
i2s1_bus: i2s1-bus {
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
<1 RK_PA1 1 &pcfg_pull_none>,
<1 RK_PA2 1 &pcfg_pull_none>,
<1 RK_PA3 1 &pcfg_pull_none>,
<1 RK_PA4 1 &pcfg_pull_none>,
<1 RK_PA5 1 &pcfg_pull_none>;
};
};
lcdc {
lcdc_dclk: lcdc-dclk {
rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
};
lcdc_den: lcdc-den {
rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
};
lcdc_hsync: lcdc-hsync {
rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
};
lcdc_vsync: lcdc-vsync {
rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
};
lcdc_rgb24: lcdc-rgb24 {
rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
<2 RK_PB5 1 &pcfg_pull_none>,
<2 RK_PB6 1 &pcfg_pull_none>,
<2 RK_PB7 1 &pcfg_pull_none>,
<2 RK_PC0 1 &pcfg_pull_none>,
<2 RK_PC1 1 &pcfg_pull_none>,
<2 RK_PC2 1 &pcfg_pull_none>,
<2 RK_PC3 1 &pcfg_pull_none>,
<2 RK_PC4 1 &pcfg_pull_none>,
<2 RK_PC5 1 &pcfg_pull_none>,
<2 RK_PC6 1 &pcfg_pull_none>,
<2 RK_PC7 1 &pcfg_pull_none>,
<2 RK_PD0 1 &pcfg_pull_none>,
<2 RK_PD1 1 &pcfg_pull_none>;
};
};
nfc {
flash_ale: flash-ale {
rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
};
flash_cle: flash-cle {
rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
};
flash_wrn: flash-wrn {
rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
};
flash_rdn: flash-rdn {
rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
};
flash_rdy: flash-rdy {
rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
};
flash_cs0: flash-cs0 {
rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
};
flash_dqs: flash-dqs {
rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
};
flash_bus8: flash-bus8 {
rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
<1 RK_PD1 1 &pcfg_pull_none>,
<1 RK_PD2 1 &pcfg_pull_none>,
<1 RK_PD3 1 &pcfg_pull_none>,
<1 RK_PD4 1 &pcfg_pull_none>,
<1 RK_PD5 1 &pcfg_pull_none>,
<1 RK_PD6 1 &pcfg_pull_none>,
<1 RK_PD7 1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
};
};
sdio {
sdio_clk: sdio-clk {
rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
};
sdio_cmd: sdio-cmd {
rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
};
sdio_pwren: sdio-pwren {
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
};
sdio_bus4: sdio-bus4 {
rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
<1 RK_PA2 2 &pcfg_pull_default>,
<1 RK_PA4 2 &pcfg_pull_default>,
<1 RK_PA5 2 &pcfg_pull_default>;
};
};
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
};
sdmmc_wp: sdmmc-wp {
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
};
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
<1 RK_PC3 1 &pcfg_pull_default>,
<1 RK_PC4 1 &pcfg_pull_default>,
<1 RK_PC5 1 &pcfg_pull_default>;
};
};
spdif {
spdif_tx: spdif-tx {
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
};
};
spi0 {
spi0_clk: spi0-clk {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
};
spi0_tx: spi0-tx {
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
};
spi0_rx: spi0-rx {
rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
};
spi1_clk: spi1-clk {
rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
};
spi1_tx: spi1-tx {
rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
};
spi1_rx: spi1-rx {
rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
};
spi1_cs1: spi1-cs1 {
rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
};
spi2_clk: spi2-clk {
rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
};
spi2_cs0: spi2-cs0 {
rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
};
spi2_tx: spi2-tx {
rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
};
spi2_rx: spi2-rx {
rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
<2 RK_PD3 2 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
<1 RK_PB2 2 &pcfg_pull_default>;
};
uart1_cts: uart1-cts {
rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
};
uart1_rts: uart1-rts {
rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
<1 RK_PC3 2 &pcfg_pull_none>;
};
uart2_cts: uart2-cts {
rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
};
uart2_rts: uart2-rts {
rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
};
};
};
};

79
arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts Normal file
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@ -0,0 +1,79 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
/dts-v1/;
#include "rv1126.dtsi"
#include "rv1126-edgeble-neu2.dtsi"
/ {
model = "Edgeble Neu2 IO Board";
compatible = "edgeble,neural-compute-module-2-io",
"edgeble,neural-compute-module-2", "rockchip,rv1126";
aliases {
serial2 = &uart2;
};
chosen {
stdout-path = "serial2:1500000n8";
};
};
&gmac {
assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
<&cru CLK_GMAC_ETHERNET_OUT>;
assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
assigned-clock-rates = <125000000>, <0>, <25000000>;
clock_in_out = "input";
phy-handle = <&phy>;
phy-mode = "rgmii";
phy-supply = <&vcc_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>;
tx_delay = <0x2a>;
rx_delay = <0x1a>;
status = "okay";
};
&mdio {
phy: ethernet-phy@0 {
compatible = "ethernet-phy-id001c.c916",
"ethernet-phy-ieee802.3-c22";
reg = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&eth_phy_rst>;
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
ethernet {
eth_phy_rst: eth-phy-rst {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
rockchip,default-sample-phase = <90>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr104;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&uart2 {
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
*/
/ {
compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
aliases {
mmc0 = &emmc;
};
vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vccio_flash: vccio-flash-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&flash_vol_sel>;
regulator-name = "vccio_flash";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_3v3>;
};
sdio_pwrseq: pwrseq-sdio {
compatible = "mmc-pwrseq-simple";
clocks = <&rk809 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
rockchip,default-sample-phase = <90>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vccio_flash>;
status = "okay";
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc_buck5>;
vcc6-supply = <&vcc_buck5>;
vcc7-supply = <&vcc5v0_sys>;
vcc8-supply = <&vcc3v3_sys>;
vcc9-supply = <&vcc5v0_sys>;
regulators {
vdd_npu_vepu: DCDC_REG1 {
regulator-name = "vdd_npu_vepu";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1350000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc3v3_sys: DCDC_REG4 {
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_buck5: DCDC_REG5 {
regulator-name = "vcc_buck5";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <2200000>;
};
};
vcc_0v8: LDO_REG1 {
regulator-name = "vcc_0v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc1v8_pmu: LDO_REG2 {
regulator-name = "vcc1v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd0v8_pmu: LDO_REG3 {
regulator-name = "vcc0v8_pmu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <800000>;
};
};
vcc_1v8: LDO_REG4 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_dovdd: LDO_REG5 {
regulator-name = "vcc_dovdd";
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_dvdd: LDO_REG6 {
regulator-name = "vcc_dvdd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_avdd: LDO_REG7 {
regulator-name = "vcc_avdd";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd: LDO_REG8 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_sd: LDO_REG9 {
regulator-name = "vcc3v3_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_5v0: SWITCH_REG1 {
regulator-name = "vcc_5v0";
};
vcc_3v3: SWITCH_REG2 {
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
};
};
};
};
&pinctrl {
bt {
bt_enable: bt-enable {
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
flash {
flash_vol_sel: flash-vol-sel {
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
wifi {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {
pmuio0-supply = <&vcc1v8_pmu>;
pmuio1-supply = <&vcc3v3_sys>;
vccio1-supply = <&vccio_flash>;
vccio2-supply = <&vccio_sd>;
vccio3-supply = <&vcc_1v8>;
vccio4-supply = <&vcc_dovdd>;
vccio5-supply = <&vcc_1v8>;
vccio6-supply = <&vcc_1v8>;
vccio7-supply = <&vcc_dovdd>;
status = "okay";
};
&saradc {
vref-supply = <&vcc_1v8>;
status = "okay";
};
&sdio {
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
max-frequency = <100000000>;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
rockchip,default-sample-phase = <90>;
sd-uhs-sdr104;
vmmc-supply = <&vcc3v3_sys>;
vqmmc-supply = <&vcc_1v8>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
status = "okay";
bluetooth {
compatible = "qcom,qca9377-bt";
clocks = <&rk809 1>;
enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */
max-speed = <2000000>;
pinctrl-names = "default";
pinctrl-0 = <&bt_enable>;
vddxo-supply = <&vcc3v3_sys>;
vddio-supply = <&vcc_1v8>;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <dt-bindings/pinctrl/rockchip.h>
#include <arm64/rockchip/rockchip-pinconf.dtsi>
/*
* This file is auto generated by pin2dts tool, please keep these code
* by adding changes at end of this file.
*/
&pinctrl {
clk_out_ethernet {
/omit-if-no-ref/
clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
rockchip,pins =
/* clk_out_ethernet_m1 */
<2 RK_PC5 2 &pcfg_pull_none>;
};
};
emmc {
/omit-if-no-ref/
emmc_rstnout: emmc-rstnout {
rockchip,pins =
/* emmc_rstn */
<1 RK_PA3 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
emmc_bus8: emmc-bus8 {
rockchip,pins =
/* emmc_d0 */
<0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d1 */
<0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d2 */
<0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d3 */
<0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d4 */
<0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d5 */
<0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d6 */
<0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
/* emmc_d7 */
<0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
emmc_clk: emmc-clk {
rockchip,pins =
/* emmc_clko */
<0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
emmc_cmd: emmc-cmd {
rockchip,pins =
/* emmc_cmd */
<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
};
};
i2c0 {
/omit-if-no-ref/
i2c0_xfer: i2c0-xfer {
rockchip,pins =
/* i2c0_scl */
<0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
/* i2c0_sda */
<0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
};
};
rgmii {
/omit-if-no-ref/
rgmiim1_pins: rgmiim1-pins {
rockchip,pins =
/* rgmii_mdc_m1 */
<2 RK_PC2 2 &pcfg_pull_none>,
/* rgmii_mdio_m1 */
<2 RK_PC1 2 &pcfg_pull_none>,
/* rgmii_rxclk_m1 */
<2 RK_PD3 2 &pcfg_pull_none>,
/* rgmii_rxd0_m1 */
<2 RK_PB5 2 &pcfg_pull_none>,
/* rgmii_rxd1_m1 */
<2 RK_PB6 2 &pcfg_pull_none>,
/* rgmii_rxd2_m1 */
<2 RK_PC7 2 &pcfg_pull_none>,
/* rgmii_rxd3_m1 */
<2 RK_PD0 2 &pcfg_pull_none>,
/* rgmii_rxdv_m1 */
<2 RK_PB4 2 &pcfg_pull_none>,
/* rgmii_txclk_m1 */
<2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txd0_m1 */
<2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txd1_m1 */
<2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txd2_m1 */
<2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txd3_m1 */
<2 RK_PA4 2 &pcfg_pull_none_drv_level_3>,
/* rgmii_txen_m1 */
<2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
};
};
sdmmc0 {
/omit-if-no-ref/
sdmmc0_bus4: sdmmc0-bus4 {
rockchip,pins =
/* sdmmc0_d0 */
<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc0_d1 */
<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc0_d2 */
<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc0_d3 */
<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc0_clk: sdmmc0-clk {
rockchip,pins =
/* sdmmc0_clk */
<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc0_cmd: sdmmc0-cmd {
rockchip,pins =
/* sdmmc0_cmd */
<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc0_det: sdmmc0-det {
rockchip,pins =
<0 RK_PA3 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
sdmmc0_pwr: sdmmc0-pwr {
rockchip,pins =
<0 RK_PC0 1 &pcfg_pull_none>;
};
};
sdmmc1 {
/omit-if-no-ref/
sdmmc1_bus4: sdmmc1-bus4 {
rockchip,pins =
/* sdmmc1_d0 */
<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc1_d1 */
<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc1_d2 */
<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
/* sdmmc1_d3 */
<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc1_clk: sdmmc1-clk {
rockchip,pins =
/* sdmmc1_clk */
<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc1_cmd: sdmmc1-cmd {
rockchip,pins =
/* sdmmc1_cmd */
<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc1_det: sdmmc1-det {
rockchip,pins =
<1 RK_PD0 2 &pcfg_pull_none>;
};
/omit-if-no-ref/
sdmmc1_pwr: sdmmc1-pwr {
rockchip,pins =
<1 RK_PD1 2 &pcfg_pull_none>;
};
};
uart0 {
/omit-if-no-ref/
uart0_xfer: uart0-xfer {
rockchip,pins =
/* uart0_rx */
<1 RK_PC2 1 &pcfg_pull_up>,
/* uart0_tx */
<1 RK_PC3 1 &pcfg_pull_up>;
};
/omit-if-no-ref/
uart0_ctsn: uart0-ctsn {
rockchip,pins =
<1 RK_PC1 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart0_rtsn: uart0-rtsn {
rockchip,pins =
<1 RK_PC0 1 &pcfg_pull_none>;
};
/omit-if-no-ref/
uart0_rtsn_gpio: uart0-rts-pin {
rockchip,pins =
<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
uart1 {
/omit-if-no-ref/
uart1m0_xfer: uart1m0-xfer {
rockchip,pins =
/* uart1_rx_m0 */
<0 RK_PB7 2 &pcfg_pull_up>,
/* uart1_tx_m0 */
<0 RK_PB6 2 &pcfg_pull_up>;
};
};
uart2 {
/omit-if-no-ref/
uart2m1_xfer: uart2m1-xfer {
rockchip,pins =
/* uart2_rx_m1 */
<3 RK_PA3 1 &pcfg_pull_up>,
/* uart2_tx_m1 */
<3 RK_PA2 1 &pcfg_pull_up>;
};
};
uart3 {
/omit-if-no-ref/
uart3m0_xfer: uart3m0-xfer {
rockchip,pins =
/* uart3_rx_m0 */
<3 RK_PC7 4 &pcfg_pull_up>,
/* uart3_tx_m0 */
<3 RK_PC6 4 &pcfg_pull_up>;
};
};
uart4 {
/omit-if-no-ref/
uart4m0_xfer: uart4m0-xfer {
rockchip,pins =
/* uart4_rx_m0 */
<3 RK_PA5 4 &pcfg_pull_up>,
/* uart4_tx_m0 */
<3 RK_PA4 4 &pcfg_pull_up>;
};
};
uart5 {
/omit-if-no-ref/
uart5m0_xfer: uart5m0-xfer {
rockchip,pins =
/* uart5_rx_m0 */
<3 RK_PA7 4 &pcfg_pull_up>,
/* uart5_tx_m0 */
<3 RK_PA6 4 &pcfg_pull_up>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/clock/rockchip,rv1126-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rockchip,rv1126-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "rockchip,rv1126";
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
};
cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
};
cpu2: cpu@f02 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf02>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
};
cpu3: cpu@f03 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf03>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
grf: syscon@fe000000 {
compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
reg = <0xfe000000 0x20000>;
};
pmugrf: syscon@fe020000 {
compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
reg = <0xfe020000 0x1000>;
pmu_io_domains: io-domains {
compatible = "rockchip,rv1126-pmu-io-voltage-domain";
status = "disabled";
};
};
qos_emmc: qos@fe860000 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe860000 0x20>;
};
qos_nandc: qos@fe860080 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe860080 0x20>;
};
qos_sfc: qos@fe860200 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe860200 0x20>;
};
qos_sdio: qos@fe86c000 {
compatible = "rockchip,rv1126-qos", "syscon";
reg = <0xfe86c000 0x20>;
};
gic: interrupt-controller@feff0000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0xfeff1000 0x1000>,
<0xfeff2000 0x2000>,
<0xfeff4000 0x2000>,
<0xfeff6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
pmu: power-management@ff3e0000 {
compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
reg = <0xff3e0000 0x1000>;
power: power-controller {
compatible = "rockchip,rv1126-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@RV1126_PD_NVM {
reg = <RV1126_PD_NVM>;
clocks = <&cru HCLK_EMMC>,
<&cru CLK_EMMC>,
<&cru HCLK_NANDC>,
<&cru CLK_NANDC>,
<&cru HCLK_SFC>,
<&cru HCLK_SFCXIP>,
<&cru SCLK_SFC>;
pm_qos = <&qos_emmc>,
<&qos_nandc>,
<&qos_sfc>;
#power-domain-cells = <0>;
};
power-domain@RV1126_PD_SDIO {
reg = <RV1126_PD_SDIO>;
clocks = <&cru HCLK_SDIO>,
<&cru CLK_SDIO>;
pm_qos = <&qos_sdio>;
#power-domain-cells = <0>;
};
};
};
i2c0: i2c@ff3f0000 {
compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
reg = <0xff3f0000 0x1000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
rockchip,grf = <&pmugrf>;
clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart1: serial@ff410000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff410000 0x100>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 7>, <&dmac 6>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
pmucru: clock-controller@ff480000 {
compatible = "rockchip,rv1126-pmucru";
reg = <0xff480000 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
cru: clock-controller@ff490000 {
compatible = "rockchip,rv1126-cru";
reg = <0xff490000 0x1000>;
clocks = <&xin24m>;
clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
dmac: dma-controller@ff4e0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xff4e0000 0x4000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
};
uart0: serial@ff560000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff560000 0x100>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 5>, <&dmac 4>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@ff570000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff570000 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 9>, <&dmac 8>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@ff580000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff580000 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 11>, <&dmac 10>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart3m0_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart4: serial@ff590000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff590000 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 13>, <&dmac 12>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart4m0_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart5: serial@ff5a0000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff5a0000 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 15>, <&dmac 14>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart5m0_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
saradc: adc@ff5e0000 {
compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
reg = <0xff5e0000 0x100>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC_P>;
reset-names = "saradc-apb";
status = "disabled";
};
timer0: timer@ff660000 {
compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
reg = <0xff660000 0x20>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
clock-names = "pclk", "timer";
};
gmac: ethernet@ffc40000 {
compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
reg = <0xffc40000 0x4000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
rockchip,grf = <&grf>;
clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
<&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
<&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
<&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"aclk_mac", "pclk_mac",
"clk_mac_speed", "ptp_ref";
resets = <&cru SRST_GMAC_A>;
reset-names = "stmmaceth";
snps,mixed-burst;
snps,tso;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "disabled";
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <4>;
snps,rd_osr_lmt = <8>;
snps,blen = <0 0 0 0 16 8 4>;
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
};
emmc: mmc@ffc50000 {
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0xffc50000 0x4000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <200000000>;
power-domains = <&power RV1126_PD_NVM>;
status = "disabled";
};
sdmmc: mmc@ffc60000 {
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0xffc60000 0x4000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <200000000>;
status = "disabled";
};
sdio: mmc@ffc70000 {
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0xffc70000 0x4000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <200000000>;
power-domains = <&power RV1126_PD_SDIO>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rv1126-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmugrf>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio0: gpio@ff460000 {
compatible = "rockchip,gpio-bank";
reg = <0xff460000 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@ff620000 {
compatible = "rockchip,gpio-bank";
reg = <0xff620000 0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@ff630000 {
compatible = "rockchip,gpio-bank";
reg = <0xff630000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@ff640000 {
compatible = "rockchip,gpio-bank";
reg = <0xff640000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@ff650000 {
compatible = "rockchip,gpio-bank";
reg = <0xff650000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
#include "rv1126-pinctrl.dtsi"